DCT

2:19-cv-10668

Cedar Lane Tech Inc v. AEE Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:19-cv-10668, C.D. Cal., 12/17/2019
  • Venue Allegations: Venue is alleged to be proper because Defendant is incorporated in California, has an established place of business in the Central District, and has committed the alleged acts of patent infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s imaging technology products infringe two patents related to methods and systems for interfacing image sensors with memory and data processing hardware.
  • Technical Context: The technology concerns the architecture of digital imaging systems, such as digital cameras and scanners, focusing on how raw image data is buffered and transferred from a sensor to a compression engine or host processor.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
1999-06-01 Priority Date for U.S. Patent No. 6,473,527
2000-01-21 Priority Date for U.S. Patent No. 6,972,790
2002-10-29 U.S. Patent No. 6,473,527 Issues
2005-12-06 U.S. Patent No. 6,972,790 Issues
2019-12-17 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued October 29, 2002 (’527 Patent)

The Invention Explained

  • Problem Addressed: The patent’s background describes a problem in conventional digital imaging systems where an "extra memory" buffer was required to sit between an analog-to-digital (A/D) converter and a JPEG compression integrated circuit (’527 Patent, col. 2:26-36). This extra memory was needed to re-organize the serial, line-by-line data stream from the image sensor into the block-based format (e.g., 8x8 pixels) required by the JPEG algorithm, adding cost and architectural complexity (’527 Patent, col. 2:41-48).
  • The Patented Solution: The invention proposes an interface module that eliminates the need for this separate, external memory buffer. The module includes its own memory, sized to store a small, predetermined number of image lines (e.g., eight lines). A read control device fills this memory from the A/D converter, and then an output control device reads an image block (e.g., 8x8 pixels) from this memory and sends it directly to the JPEG compression device. (’527 Patent, Abstract; col. 3:1-18). This process manages the data format conversion without a large, secondary RAM buffer.
  • Technical Importance: This design sought to reduce the component count, cost, and complexity of digital imaging hardware like scanners and cameras by integrating the block-formatting memory function into a dedicated interface module (’527 Patent, col. 2:44-48, 52-56).

Key Claims at a Glance

  • The complaint asserts "exemplary claims" from the ’527 Patent but does not specify them in the body of the complaint, instead referencing an external exhibit (Compl. ¶19). Independent claims of the patent are Claim 1 (a module) and Claim 8 (a method).
  • Independent Claim 1 recites a module comprising:
    • A read control means for reading a predetermined number of image lines and generating a control signal.
    • A memory means for storing those image lines, where the memory is capable of storing the same number of lines as a "built-in memory device" within the JPEG compression means.
    • An output control means that responds to the control signal by reading an image block from the memory means and forwarding it to the JPEG compression means' built-in memory. (’527 Patent, col. 4:55 - col. 5:11).
  • The complaint reserves the right to assert additional claims (Compl. ¶21).

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued December 6, 2005 (’790 Patent)

The Invention Explained

  • Problem Addressed: The patent describes the incompatibility between the continuous, fixed-rate "video style output" of an image sensor and the asynchronous, on-demand data access model of a microprocessor (’790 Patent, col. 1:46-53). Bridging this gap typically required "additional glue logic" and custom interface circuitry, which undermines the cost and integration benefits of CMOS system-on-a-chip (SoC) designs (’790 Patent, col. 1:53-63).
  • The Patented Solution: The patent discloses an interface, preferably integrated on the same die as the image sensor, that decouples the sensor from the host processor. The interface uses a memory buffer (such as a FIFO) to store image data as it arrives from the sensor. A signal generator monitors the amount of data in the buffer and, when a certain quantity is reached, sends a signal (e.g., an interrupt) to the processor. A control circuit then manages the transfer of the buffered data to the system bus at a rate determined by the processor, not the sensor. (’790 Patent, Abstract; col. 2:4-13).
  • Technical Importance: This architecture enables a processor to efficiently retrieve image data without being slaved to the sensor's rigid timing, facilitating higher levels of integration and reducing the need for external interface components in imaging systems (’790 Patent, col. 2:25-30).

Key Claims at a Glance

  • The complaint asserts "exemplary claims" from the ’790 Patent by reference to an external exhibit (Compl. ¶29). Independent claims of the patent are Claim 1 (an interface) and Claim 15 (an integrated circuit).
  • Independent Claim 1 recites an interface comprising:
    • A memory for storing imaging array data at a rate determined by the sensor's clocking signals.
    • A signal generator that generates a signal for the processor system "in response to the quantity of data in the memory."
    • A circuit for controlling the transfer of data from the memory at a rate determined by the processor system. (’790 Patent, col. 8:5-18).
  • The complaint reserves the right to assert additional claims (Compl. ¶23).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies the accused instrumentalities as the "Exemplary AEE Technology Products," which are detailed in charts incorporated by reference but not attached to the complaint as filed (Compl. ¶¶ 13, 23).
  • Functionality and Market Context: The complaint alleges, in a conclusory manner, that the accused products "practice the technology claimed" by the patents-in-suit (Compl. ¶¶ 19, 29). It further alleges that Defendant makes, uses, sells, and imports these products, and that its own employees internally test them (Compl. ¶¶ 13-14). The complaint does not provide specific, non-conclusory details about the technical operation or architecture of the accused products in its main body. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges infringement but incorporates the specific analysis by reference to Exhibits 3 and 4, which were not included with the filed complaint document (Compl. ¶¶ 19, 29). The narrative infringement theory is summarized below.

  • ’527 Patent Infringement Allegations: The complaint alleges that the "Exemplary AEE Technology Products" directly infringe one or more claims of the ’527 Patent (Compl. ¶13). It states that the charts in Exhibit 3 compare the patent claims to the products and that, based on these charts, the products "satisfy all elements of the Exemplary '527 Patent Claims" (Compl. ¶19).

  • Identified Points of Contention:

    • Architectural Questions: A primary question may be whether the architecture of the accused products maps onto the specific three-part structure of Claim 1 ("read control means", "memory means", "output control means"). The analysis may focus on whether these are distinct functional blocks in the accused products or if their functions are integrated in a manner that differs from the claimed configuration.
    • Technical Questions: A key technical question may be whether the accused products contain a memory element that is "capable of storing the same number of image lines" as a separate "built-in memory device" of a JPEG compressor. Evidence of this specific 1-to-1 relationship in memory sizing will likely be a point of focus.

  • ’790 Patent Infringement Allegations: The complaint alleges that the "Exemplary AEE Technology Products" directly infringe one or more claims of the ’790 Patent (Compl. ¶23). It incorporates by reference the claim charts in Exhibit 4, which it asserts show that the products "practice the technology claimed" by the patent and "satisfy all elements of the Exemplary '790 Patent Claims" (Compl. ¶29).

  • Identified Points of Contention:

    • Scope Questions: A potential dispute concerns the scope of the phrase "in response to the quantity of data in the memory." The question is whether the accused products' trigger for alerting the processor (e.g., a DMA controller or interrupt) is based on the fill level of a buffer, or if it is based on a different event, such as the completion of a full frame transfer.
    • Technical Questions: An evidentiary question will be whether the data transfer from the buffer to the processor in the accused products is controlled "at a rate determined by the processor system," as required by Claim 1. This distinguishes it from a transfer rate dictated by the image sensor, suggesting the need for evidence of asynchronous, processor-led data bursts.

V. Key Claim Terms for Construction

  • ’527 Patent: "memory means...capable of storing the same number of image lines as said built-in memory device" (from Claim 1)

    • Context and Importance: This term is critical because it defines a specific structural and capacity relationship between two distinct memory components. The infringement analysis will likely turn on whether the accused products possess two such memories and if they have this claimed relationship.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A party could argue that "means" can refer to logically distinct partitions within a single physical memory, not necessarily separate chips. The phrase "capable of storing" might be interpreted to mean the capacity is at least equal to, not strictly identical to, the built-in memory. The specification refers generally to "a memory device 24" without mandating a specific physical form (’527 Patent, col. 3:3-4).
      • Evidence for a Narrower Interpretation: The patent's stated goal is to save an "extra memory device" (’527 Patent, col. 2:44-48). This context suggests the "memory means" and the "built-in memory device" are architecturally separate components. The abstract states the memory "can save the same number of image lines," which a party could argue implies an identical, not just sufficient, capacity to support the block-based handoff.

  • ’790 Patent: "a signal...in response to the quantity of data in the memory" (from Claim 1)

    • Context and Importance: This term defines the trigger for communication between the imaging interface and the host processor. Practitioners may focus on this term because if the signal is triggered by an event other than the "quantity of data" (e.g., a "frame complete" flag), infringement may be avoided.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification discloses an embodiment where an interrupt generator compares a FIFO counter ("Sc") to a FIFO limit ("SL") and asserts a signal if "Sc >= SL" (’790 Patent, col. 6:11-14). This supports an interpretation where a signal generated upon a buffer's fill-level reaching a set watermark meets the "in response to the quantity" limitation.
      • Evidence for a Narrower Interpretation: A party could argue the phrase requires a direct causal link to the fill level itself, not merely a temporal correlation. For example, a signal that is generated only upon receipt of an entire frame, irrespective of the buffer's fill level during the frame's acquisition, might be argued to fall outside the scope of the claim.

VI. Other Allegations

  • Indirect Infringement: For both the ’527 and ’790 patents, the complaint alleges induced infringement based on Defendant distributing "product literature and website materials" that allegedly instruct customers on how to use the products in an infringing manner (Compl. ¶¶ 17, 27). It also alleges contributory infringement, asserting the products are not staple articles of commerce suitable for substantial noninfringing use (Compl. ¶¶ 18, 28).
  • Willful Infringement: The complaint alleges that service of the complaint constitutes actual knowledge of infringement for both patents (Compl. ¶¶ 15, 25). It alleges that despite this knowledge, Defendant's infringing conduct is ongoing, which may support a claim for post-filing willful infringement (Compl. ¶¶ 16, 26). No allegations of pre-suit knowledge are made.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of "architectural mapping": Do the integrated System-on-a-Chip designs in AEE’s modern imaging products contain the distinct, sequentially-operating components ("read control means", "memory means", "output control means") recited in the '527 patent, or has technological evolution resulted in a fundamentally different architecture that does not map onto the claim elements?
  • A key dispute for the '790 patent will concern the "functional trigger" for data transfer. Does the accused system alert the host processor "in response to the quantity of data" in a buffer as claimed, or is the transfer initiated by a different event, such as a frame-completion signal, raising the question of whether the accused functionality meets the specific causal requirement of the claim?
  • Given the complaint’s reliance on non-proffered exhibits for its infringement contentions, a threshold question will be the "evidentiary basis" for infringement. What technical evidence will be produced to demonstrate that the internal operations of AEE’s products—particularly their memory management and processor communication protocols—actually perform the specific functions and possess the specific structural relationships required by the asserted claims?