DCT

2:20-cv-01824

Altair Logix LLC v. FLIR Systems Inc

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: FLIR Systems, Inc. (Oregon)
- Plaintiff’s Counsel: Budo Law P.C.
Case Identification: 2:20-cv-01824, C.D. Cal., 02/26/2020
Venue Allegations: Venue is alleged to be proper based on Defendant having a regular and established place of business within the Central District of California and having committed alleged acts of infringement in the district.
Core Dispute: Plaintiff alleges that Defendant’s thermal imaging cameras, which incorporate multi-core processors, infringe a patent related to dynamically reconfigurable circuits for processing multiple data streams.
Technical Context: The technology concerns system-on-chip architectures designed to provide the performance of fixed-function hardware with the flexibility of programmable devices for complex, real-time media processing.
Key Procedural History: The complaint notes that asserted claim 1 of the patent-in-suit was an originally filed claim that issued without amendment and without any anticipation rejections during prosecution, a point Plaintiff may use to suggest the claim's novelty and non-obviousness.

Case Timeline

Date	Event
1997-02-28	U.S. Patent No. 6,289,434 Priority Date
1998-02-27	U.S. Patent No. 6,289,434 Application Filing Date
2001-09-11	U.S. Patent No. 6,289,434 Issue Date
2015-11-21	Date of archived webpage for Accused Instrumentality
2020-02-26	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"

Patent Identification: U.S. Patent No. 6,289,434, "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates," issued September 11, 2001 (the "’434 Patent").

The Invention Explained

Problem Addressed: The patent addresses the trade-offs between different methods of implementing complex functions on integrated circuits. It posits that traditional hard-wired, fixed-function circuits offer high performance but are inflexible and costly, while alternatives like microprocessors, Digital Signal Processors (DSPs), and Field-Programmable Gate Arrays (FPGAs) suffer from deficiencies in performance, cost-effectiveness, or efficiency for certain real-time, parallel processing tasks (’434 Patent, col. 1:39-col. 2:39). Fixed-function systems in particular are described as inefficient due to "temporal redundancy," requiring dedicated silicon for all possible processing functions regardless of whether they are in use (’434 Patent, col. 2:50-57).
The Patented Solution: The invention proposes an apparatus with multiple, dynamically reconfigurable "media processing units" (MPUs). These units can be reconfigured at run-time to adapt to varying data and processing requirements, which removes redundancy by "re-using groups of computational and storage elements in different configurations" (’434 Patent, col. 3:1-4). This approach, as illustrated by the system architecture in Figure 3, aims to achieve the performance of a fixed-function implementation at a lower cost by enhancing flexibility and efficiency (’434 Patent, col. 2:64-col. 3:1).
Technical Importance: The patented technology sought to provide a new, more efficient architecture for the growing class of applications requiring high-performance, parallel processing of media streams, such as video processing, communications, and 3D graphics rendering (’434 Patent, col. 1:32-38).

Key Claims at a Glance

The complaint asserts at least independent claim 1.
The essential elements of independent claim 1 are:
- An apparatus for processing data, comprising:
- An addressable memory for storing data and instructions;
- A plurality of media processing units, each coupled to the memory;
- Each media processing unit comprising: a multiplier, an arithmetic unit, an arithmetic logic unit, and a bit manipulation unit;
- The arithmetic logic unit is capable of operating concurrently with the multiplier or the arithmetic unit;
- The bit manipulation unit is capable of operating concurrently with the arithmetic logic unit and with the multiplier or the arithmetic unit;
- Each of the plurality of media processing units is for performing an operation simultaneously with other operations by other media processing units.
The complaint’s phrasing "at least claim 1" reserves the right to assert additional claims, including dependent claims. (Compl. ¶26).

III. The Accused Instrumentality

Product Identification

The FLIR T1K Thermal Imaging Camera, which the complaint also refers to as the T1K/T1020 camera (the "Accused Instrumentality") (Compl. ¶¶ 26, 28).

Functionality and Market Context

The Accused Instrumentality is a high-end infrared camera designed for thermography experts, capable of capturing still images and video footage (Compl. ¶28, p.14). The complaint alleges that the camera's infringing functionality is provided by an internal component, the Digi ConnectCore® 6 system-on-module (SOM). This SOM is based on the Freescale i.MX6 processor family, which features a scalable, multi-core ARM Cortex-A9 architecture (Compl. ¶28, pp.14-15). The complaint alleges that this multi-core processor integrates several modules and circuit boards into a single, compact unit to perform the device's complex processing tasks (Compl. ¶28, p.14). A block diagram from a Digi datasheet shows the "Multi core processors" at the heart of the system (Compl. ¶28, p.16).
The complaint positions the Accused Instrumentality as a "highest-end, most complex product" that "raises the bar on performance" in its market (Compl. ¶28, pp.13-14).

IV. Analysis of Infringement Allegations

’434 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An apparatus for processing data, comprising: an addressable memory for storing the data, and a plurality of instructions...	The Accused Instrumentality's memory system, which is part of the Digi ConnectCore 6 module and provides instructions and data to the processors. A block diagram shows various memory interfaces (e.g., DDR3, eMMC) (Compl. ¶28, p.17).	¶27	col. 55:21-25
a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs...	The multiple ARM Cortex-A9 processor cores within the Digi ConnectCore 6 module. The complaint asserts each core acts as a media processing unit (Compl. ¶28). A block diagram shows these "Multi core processors" connected to the memory system (Compl. ¶28, p.17).	¶28	col. 55:26-30
each media processing unit...comprising: a multiplier...	The NEON media coprocessor within each ARM Cortex-A9 core, which is alleged to comprise a multiplier (e.g., an Integer MUL or FP MUL). A diagram of the NEON architecture is provided showing an "FP MUL" unit (Compl. ¶29, p.24).	¶29	col. 55:31-36
an arithmetic unit...	The NEON media coprocessor, which is alleged to comprise an arithmetic unit (e.g., an FP ADD). A diagram shows the "FP ADD" unit in parallel with the multiplier (Compl. ¶30, p.24).	¶30	col. 55:37-41
an arithmetic logic unit...capable of operating concurrently with at least one selected from the multiplier and arithmetic unit;	The NEON media coprocessor, which is alleged to comprise an arithmetic logic unit (e.g., an Integer ALU). The complaint alleges it can operate concurrently with the multiplier or arithmetic unit based on a diagram showing them as parallel functional units (Compl. ¶31, p.26).	¶31	col. 56:6-12
a bit manipulation unit...capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit;	The NEON media coprocessor, which is alleged to comprise a bit manipulation unit (e.g., an Integer Shift unit). The complaint alleges concurrent operation based on the parallel hardware structure shown in a diagram (Compl. ¶32, p.28).	¶32	col. 56:13-20
each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units...	The multiple ARM Cortex-A9 cores on the chip operating simultaneously. The complaint points to marketing materials describing the "Scalable Cortex-A9 multi-core performance" of the Accused Instrumentality's processor (Compl. ¶33, p.32).	¶33	col. 56:21-25

Identified Points of Contention:
- Scope Questions: The '434 Patent repeatedly distinguishes its "new apparatus" from prior art microprocessors and describes its core innovation as the ability to "adaptively dynamically reconfigur[e] groups of computational and storage elements in run-time" (’434 Patent, col. 3:14-18, col. 2:64-col. 3:8). The infringement case may raise the question of whether a standard, off-the-shelf ARM Cortex-A9 processor, which has a fixed architecture rather than one based on run-time reconfiguration of its core elements, falls within the scope of the claimed "media processing unit."
- Technical Questions: Claim 1 requires four distinct sub-components within each MPU: a multiplier, an arithmetic unit, an ALU, and a bit manipulation unit. The complaint maps these to specific functional blocks within the ARM NEON engine (e.g., "FP ADD" for arithmetic unit, "Integer Shift" for bit manipulation unit) (Compl. ¶¶ 29-32). A factual question for the court will be whether these specific hardware blocks in a general-purpose SIMD engine perform the functions of the claimed units as understood in the context of the patent, and whether they are indeed distinct components as claimed. For instance, what evidence demonstrates that the "Integer Shift unit" is a "bit manipulation unit" separate from the general capabilities of the "arithmetic logic unit"?

V. Key Claim Terms for Construction

The Term: "media processing unit"
Context and Importance: This term is the central building block of the claimed invention. Its construction is critical, as it will likely determine whether a general-purpose, multi-core CPU can be considered an infringing structure. Practitioners may focus on this term because the patent's specification describes it as an "aggregate of the dynamically reconfigurable computational and storage elements" (’434 Patent, col. 3:15-17), which may be a narrower definition than what is required to read on the accused ARM processor core.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The body of claim 1 itself defines the "media processing unit" by listing its required sub-components (multiplier, AU, ALU, BMU). A party could argue that any structure containing these components and meeting the functional requirements is a "media processing unit," regardless of its commercial name or whether it is described as "reconfigurable."
- Evidence for a Narrower Interpretation: The specification explicitly states the invention is a "new apparatus" that solves problems of prior art microprocessors and DSPs by "re-using groups of computational and storage elements in different configurations" at run-time (’434 Patent, col. 3:2-8). This repeated emphasis on dynamic reconfigurability as the core inventive concept could support a narrower construction that excludes fixed-architecture CPU cores.
The Term: "arithmetic unit"
Context and Importance: Claim 1 recites an "arithmetic unit" and an "arithmetic logic unit" (ALU) as separate and distinct elements. The complaint maps these to an "FP ADD" unit and an "Integer ALU," respectively (Compl. ¶¶ 30-31). The viability of the infringement theory depends on whether the patent supports this distinction. If "arithmetic unit" is construed to be indistinct from or encompassed by the "arithmetic logic unit," the claim could face challenges for indefiniteness under 35 U.S.C. § 112.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation (supporting distinction): The patent describes two main computational units within an MPU: a "32 bit Multiplier whose output can be accumulated to 64 bits (MAU) and a 32 bit Arithmetic Logic Unit (ALU)" (’434 Patent, col. 13:53-56). A party could argue that Claim 1 deliberately separated the "multiplier" from the accumulator/adder function of the MAU, with the latter constituting the "arithmetic unit" distinct from the general-purpose ALU.
- Evidence for a Narrower Interpretation (challenging distinction): The term "arithmetic logic unit" inherently includes arithmetic functions. A party could argue that reciting a separate "arithmetic unit" is redundant. The specification does not appear to provide an explicit definition for "arithmetic unit" that clearly separates its function from the described ALU, beyond listing them as separate components in the claim language itself.

VI. Other Allegations

Indirect Infringement: The complaint does not include counts for indirect or induced infringement and focuses its allegations on direct infringement by Defendant (Compl. ¶26).
Willful Infringement: The complaint does not explicitly plead willful infringement or allege that Defendant had pre-suit knowledge of the ’434 Patent. It alleges only constructive notice "by operation of law" (Compl. ¶37).

VII. Analyst’s Conclusion: Key Questions for the Case

A core issue will be one of definitional scope: can the term "media processing unit," which the ’434 Patent specification defines in the context of a novel, dynamically reconfigurable architecture, be construed broadly enough to read on a standard, off-the-shelf ARM processor core with a fixed architecture?
A key evidentiary question will be one of technical correspondence: does the accused product's standard ARM NEON engine, with its specific functional blocks for integer and floating-point operations, contain the four distinct components—a multiplier, an arithmetic unit, an arithmetic logic unit, and a bit manipulation unit—as structurally and functionally required by the unique language of Claim 1?
A central claim construction dispute will likely focus on distinctness: does the intrinsic evidence of the '434 Patent provide a clear and distinct definition for an "arithmetic unit" separate from an "arithmetic logic unit," a distinction necessary to support both the infringement allegation and the validity of the claim against potential indefiniteness challenges.