InnoMemory LLC v. Kingston Technology Co Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: InnoMemory LLC (Texas)
  • Defendant: Kingston Technology Company, Inc. (Delaware)
  • Plaintiff’s Counsel: Insight, PLC; Ni, Wang & Massand, PLLC
• Case Identification: 2:21-cv-05798, C.D. Cal., 07/19/21
• Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains a place of business in the district and has committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s DDR3 and DDR4 memory products infringe a patent related to methods for retrieving data words from a random access memory integrated circuit.
• Technical Context: The technology concerns the architecture of high-performance Dynamic Random Access Memory (DRAM), focusing on optimizing power consumption and speed by varying how data is retrieved during random versus sequential (burst) read operations.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with pre-suit notice of infringement on January 28, 2019, including a letter that identified the patent-in-suit and attached a claim chart detailing the alleged infringement.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "Integrated Circuit Random Access Memory Capable of Reading Either One or More Than One Data Word in a Single Clock Cycle"

• Patent Identification: U.S. Patent No. 6,240,046 (“’046 Patent”), “Integrated Circuit Random Access Memory Capable of Reading Either One or More Than One Data Word in a Single Clock Cycle,” issued May 29, 2001.

The Invention Explained

• Problem Addressed: The patent describes a challenge in memory design where different types of memory access have different efficiency requirements. For random memory reads, retrieving only the single requested data word saves power compared to retrieving multiple words, where the additional words would be discarded. Conversely, for sequential (burst) reads, retrieving multiple words in one operation is more power-efficient than performing multiple separate single-word read operations. The patent identifies an "unfilled need for memory devices with low power consumption characteristics" that can adapt to these different scenarios. (’046 Patent, col. 2:1-15).
• The Patented Solution: The invention is a random access memory architecture that can operate flexibly. The specification describes circuitry, such as a flip-flop, that allows the memory to switch between two states: one where it retrieves a single data word in a clock cycle for random reads, and another where it retrieves more than one data word in a clock cycle for burst reads. (’046 Patent, Abstract; col. 2:45-56). By matching the retrieval method to the type of read request, the architecture aims to achieve lower average power consumption. (’046 Patent, col. 2:57-65).
• Technical Importance: This approach seeks to provide a "best of both worlds" solution, combining the performance advantages of multi-word burst reads with the power-saving benefits of single-word random reads in a single integrated circuit. (’046 Patent, col. 3:1-21).

Key Claims at a Glance

• The complaint asserts at least independent claim 1. (Compl. ¶6).
• The essential elements of independent claim 1 are:
  • A random access memory integrated circuit, comprising:
  • a memory array capable of storing a plurality of data words;
  • a data bus coupled to the memory array, the data bus having a width of more than one data word;
  • wherein the random access memory integrated circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle, the first data word and the second data word each being any of the plurality of data words.

III. The Accused Instrumentality

Product Identification

• The complaint identifies "DDR3 and DDR4 random access memory" products as the accused instrumentalities. (Compl. ¶6). It provides Defendant’s "Server Premier DDR4 SDRAM KSM29ES8/8HD" as an exemplary product. (Compl. ¶8). A screenshot from Defendant's website shows a product category titled "Memory for Servers, Desktops, and Laptops" which includes the exemplary product. (Compl. p. 5).

Functionality and Market Context

• The complaint alleges the accused products are high-speed dynamic random-access memories that utilize a "double data rate (DDR) architecture." (Compl. ¶8). This architecture is described as an "8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the DQ I/O pins." (Compl. ¶8). A provided product datasheet for the exemplary KSM29ES8/8HD module specifies it as "8GB 1Rx8 1G x 72-Bit PC4-2933 CL21 288-Pin DIMM." (Compl. p. 6). The allegations rely on the functionality defined by the JEDEC industry standard for DDR4 SDRAM to describe the operation of the accused products. (Compl. p. 7).

IV. Analysis of Infringement Allegations

’046 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: The infringement theory may raise a significant question of claim scope regarding the final "wherein" clause of claim 1. The claim recites retrieving a first data word "in a first clock cycle" and a second data word "in a second clock cycle." The complaint, however, describes the accused DDR technology as retrieving two data words "in one clock cycle," with one word transferred on the positive clock edge and the other on the negative clock edge. (Compl. ¶8). The court will need to determine if the claim language requiring two separate clock cycles for the retrieval of two data words can be construed to read on a DDR architecture that retrieves two data words within a single clock cycle.
  • Technical Questions: A central technical question will be whether the operational mechanics of DDR memory, which transfers data on both the rising and falling edges of a clock signal, align with the claimed sequence of events. The complaint's own infringement allegation appears to describe a technical operation (two words per cycle) that is facially different from the claim's recitation (one word per cycle, over two consecutive cycles). The evidentiary basis for how the accused product's operation maps to the claim language will be a focus of dispute.

V. Key Claim Terms for Construction

• The Term: "retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle"

• Context and Importance: The construction of this entire phrase will be critical to the dispute. Practitioners may focus on this term because the plaintiff’s infringement theory depends on mapping the DDR architecture, which retrieves data on both edges of a single clock signal, onto this claim language that specifies events occurring in two distinct and sequential clock cycles.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent states the invention is "capable" of this two-cycle retrieval, which a party might argue does not preclude other modes of operation. (’046 Patent, col. 2:25-28). The specification's discussion of "burst read cycles" involving a "number of sequential read operations" could be cited to support a more flexible interpretation of how data is retrieved over multiple clock ticks. (’046 Patent, col. 3:1-4).
  • Evidence for a Narrower Interpretation: The claim language explicitly separates the retrieval of the first and second data words into a "first clock cycle" and a "second clock cycle." A party could argue this language requires two temporally distinct clock periods. The patent's abstract distinguishes between retrieving "one data word in a single clock cycle" and "more than one data word in a single clock cycle," which suggests the patentee understood how to describe multi-word retrieval within a single cycle and drafted claim 1 differently. (’046 Patent, Abstract).

VI. Other Allegations

• Indirect Infringement: The prayer for relief requests a judgment that Defendant "induced others to infringe the '046 Patent." (Compl. p. 13, ¶1). However, the body of the complaint focuses on direct infringement and does not plead specific facts to support the knowledge and intent elements required for a claim of induced infringement.

• Willful Infringement: The complaint alleges willful infringement based on Defendant having "actual knowledge of the '046 Patent since at least as early as January 31, 2019." (Compl. ¶9). This allegation is based on a pre-suit notice letter Plaintiff sent to Defendant, which allegedly included a copy of the patent and a claim chart detailing infringement. (Compl. ¶4, p. 4; ¶9).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case will likely depend on the answers to two central questions:

1. A core issue will be one of claim construction: Can the phrase "in a first clock cycle and... in a second clock cycle," which implies two sequential and distinct time periods, be interpreted to cover the Double Data Rate (DDR) architecture, where two data words are transferred on the rising and falling edges of a single clock cycle?

2. A key evidentiary question will be one of infringement mapping: Does the factual operation of the accused DDR3 and DDR4 memory products, as described by industry standards and the complaint itself, correspond to the specific sequence of operations required by Claim 1, or is there a fundamental mismatch between the technology's operation and the claim's language?