DCT

2:22-cv-05747

Bell Semiconductor LLC v. NVIDIA Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: *Bell Semiconductor, LLC v. NVIDIA Corporation*, 2:22-cv-05747, C.D. Cal., 12/07/2022
  • Venue Allegations: Venue is alleged based on Defendants having committed acts of infringement and maintaining regular and established places of business within the Central District of California. For lead defendant NVIDIA, this includes an office in San Dimas, California.
  • Core Dispute: Plaintiff alleges that Defendants’ high-performance semiconductor chips (e.g., GPUs, SoCs) and downstream products incorporating them (e.g., graphics cards, computers, game consoles) infringe five patents related to semiconductor packaging technology.
  • Technical Context: The asserted patents concern advanced semiconductor packaging techniques designed to mitigate signal degradation, electronic noise, and physical stress failures in high-frequency, high-density integrated circuits.
  • Key Procedural History: This Second Amended Complaint follows a series of pre-suit notices sent to NVIDIA alleging infringement, with specific notice dates provided for each asserted patent, forming the basis for allegations of willful infringement.

Case Timeline

Date Event
2003-10-08 U.S. Patent No. 7,345,245 Priority Date
2006-03-17 U.S. Patent No. 7,180,011 Priority Date
2006-03-22 U.S. Patent No. 8,049,340 & 8,288,269 Priority Date
2006-04-06 U.S. Patent No. 7,646,091 Priority Date
2007-02-20 U.S. Patent No. 7,180,011 Issued
2008-03-18 U.S. Patent No. 7,345,245 Issued
2010-01-12 U.S. Patent No. 7,646,091 Issued
2011-11-01 U.S. Patent No. 8,049,340 Issued
2012-10-16 U.S. Patent No. 8,288,269 Issued
2020-03-26 Notice of ’269 Patent Infringement to NVIDIA
2021-07-30 Notice of ’091 & ’245 Patent Infringement to NVIDIA
2021-08-16 Notice of ’011 Patent Infringement to NVIDIA
2022-06-03 Notice of ’340 Patent Infringement to NVIDIA
2022-12-07 Second Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,049,340 - "Device for Avoiding Parasitic Capacitance in an Integrated Circuit Package"

The Invention Explained

  • Problem Addressed: The patent's background describes how, in high-frequency integrated circuits, unintended electrical coupling, or "parasitic capacitance," can form between different metal layers within the semiconductor package (Compl. ¶29, citing ’340 Patent, col. 2:52-60). This parasitic capacitance, particularly from large metal areas like ground planes or routing layers near contact pads, can distort the electrical signal, which "disadvantageously limited" the maximum operating frequency of the device (Compl. ¶31, citing ’340 Patent, col. 3:12-25).
  • The Patented Solution: The invention solves this problem by creating a device with specific "cutouts" in the metal layers adjacent to the primary contact pad layer (Compl. ¶32). These cutouts are voids in the metal that are designed to completely surround the area under each high-frequency contact pad, thereby "substantially avoid[ing] overlap" and minimizing the parasitic capacitance that would otherwise form (Compl. ¶32; ’340 Patent, col. 4:51-62).
  • Technical Importance: By reducing signal distortion, this packaging structure allows integrated circuits to operate reliably at higher frequencies than prior art designs (Compl. ¶35).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claim 2 (Compl. ¶33-34).
  • Essential elements of independent claim 1 include:
    • An integrated circuit package substrate comprising:
    • a first and a second electrically conductive layer separated by an insulating layer with no intermediate conductive layer;
    • a plurality of rows of contact pads in the first layer;
    • a plurality of cutouts in the second layer for reducing parasitic capacitance;
    • wherein each cutout encloses an electrically insulating area; and
    • wherein each such insulating area "completely overlaps" a corresponding contact pad, resulting in "substantially no overlap" of the contact pads with metal in the second layer.
  • The complaint does not explicitly reserve the right to assert other dependent claims.

U.S. Patent No. 8,288,269 - "Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package"

The Invention Explained

  • Problem Addressed: This patent is a divisional of the '340 patent and shares an identical specification, thus addressing the same problem of performance-limiting parasitic capacitance in multi-layer semiconductor packages (Compl. ¶38).
  • The Patented Solution: Where the '340 patent claims the physical apparatus, the '269 patent claims the method of manufacturing it (Compl. ¶38). The invention is a multi-step process that involves sequentially forming the various conductive and insulating layers, including the step of forming a "plurality of cutouts" in a conductive layer that completely overlap the contact pads to eliminate substantial metal overlap (Compl. ¶38-39).
  • Technical Importance: The method claims provide a different scope of protection, covering the manufacturing process itself rather than just the final product, which is a common strategy to create a more robust patent portfolio (Compl. ¶41).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claim 2 (Compl. ¶39-40).
  • Essential elements of independent claim 1 include:
    • A method, comprising steps of:
    • forming a first electrically conductive layer with contact pads;
    • forming an insulating layer on the first layer; and
    • forming a second conductive layer over the insulating layer, where this second layer includes metal and a plurality of cutouts that enclose insulating areas that "completely overlap" the contact pads.
  • The complaint does not explicitly reserve the right to assert other dependent claims.

U.S. Patent No. 7,646,091 - "Semiconductor Package and Method Using Isolated Vss Plane to Accommodate High Speed Circuitry Ground Isolation"

  • Technology Synopsis: The complaint states that when high-speed and low-speed circuitry share a common ground plane, electrical noise from the high-speed portion can interfere with the low-speed portion, causing "cross-talk and ground-bounce" (Compl. ¶44, 47). The patent teaches a solution using multiple, electrically isolated ground planes within the same package—one dedicated to the high-speed circuitry and another for the low-speed circuitry—to prevent this interference (Compl. ¶45).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶46).
  • Accused Features: The complaint accuses NVIDIA's ConnectX series ethernet chip products, such as the ConnectX-4 Lx, of infringement (Compl. ¶1, 84).

U.S. Patent No. 7,345,245 - "Robust High Density Substrate Design for Thermal Cycling Reliability"

  • Technology Synopsis: The complaint explains that thin semiconductor substrates are prone to warpage from heat, creating high-stress concentrations under the corners of the die (Compl. ¶50). These stresses can cause cracks to form in the signal traces, leading to device failure (Compl. ¶50). The patent discloses a design that improves reliability by routing signal traces away from these high-stress areas, specifically prohibiting traces from being located over ball pads that are within two ball pad pitches of the die corner (Compl. ¶51-52).
  • Asserted Claims: The complaint asserts independent claims 1 and 2 (Compl. ¶52).
  • Accused Features: The complaint accuses NVIDIA products made with the Maxwell 2.0 Architecture, such as the ODNX02 SoC, and downstream products like the Nintendo Switch which incorporates such SoCs (Compl. ¶1, 94, 166).

U.S. Patent No. 7,180,011 - "Device for Minimizing Differential Pair Length Mismatch and Impedance Discontinuities in an Integrated Circuit Package"

  • Technology Synopsis: The complaint describes how in differential pair signaling (using two parallel conductors), a length mismatch between the conductors distorts the signal (Compl. ¶56). Prior attempts to add length to the shorter conductor created new "impedance discontinuity" problems (Compl. ¶57). The patent teaches a device that solves both problems simultaneously by routing the added trace length "entirely inside an area Surrounded by a contact pad" that terminates the shorter conductor (Compl. ¶58).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶59).
  • Accused Features: The complaint accuses NVIDIA's GA104 GPU of infringement (Compl. ¶1, 74).

III. The Accused Instrumentality

Product Identification

The complaint identifies three main categories of "NVIDIA Accused Product": (1) Maxwell 2.0 architecture SoCs (e.g., ODNX02); (2) Turing architecture GPUs (e.g., GA104, TU106); and (3) ConnectX series ethernet chips (e.g., ConnectX-4 LX) (Compl. ¶1). It further identifies numerous downstream products from other defendants that incorporate these chips, such as Dell computers, Gigabyte and MSI graphics cards, the Nintendo Switch, and products sold by Best Buy and Amazon (Compl. ¶1, 15-16, 64, 112).

Functionality and Market Context

The accused instrumentalities are high-performance semiconductor components that form the core of modern graphics cards, computer systems, servers, and consumer electronics (Compl. ¶1, 5). The complaint alleges that these NVIDIA chips are foundational components for a wide array of products across the electronics industry, sold by the various downstream and retailer defendants (Compl. ¶15-16).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that NVIDIA directly infringes the '340 and '269 patents by manufacturing and selling certain GPUs and SoCs. It further alleges that the other defendants directly infringe by making, using, selling, or importing downstream products that incorporate these accused NVIDIA chips. The complaint references claim chart exhibits that detail the infringement theories for each patent (e.g., Ex. E for the '340 patent, Ex. F for the '269 patent); however, these exhibits were not included with the provided complaint document. The narrative infringement theories are summarized below.

'340 Patent Infringement Allegations

The complaint alleges that NVIDIA's products, exemplified by the GP108 GPU, directly infringe the apparatus claims of the '340 patent (Compl. ¶64). The infringement theory is that the physical construction of these GPUs embodies the claimed integrated circuit package substrate. This includes the specified arrangement of conductive and insulating layers, the rows of contact pads, and, critically, the "plurality of cutouts" formed in a conductive layer that "completely overlaps" the contact pads to reduce parasitic capacitance as recited in claim 1 (Compl. ¶33, 64).

'269 Patent Infringement Allegations

The complaint alleges that NVIDIA infringes the method claims of the '269 patent by its process of manufacturing products like the GP108 GPU (Compl. ¶104). The theory is that NVIDIA's manufacturing methods necessarily perform the claimed steps, which include forming a first conductive layer with contact pads and subsequently forming a second conductive layer containing the specific capacitance-reducing cutouts claimed in the patent (Compl. ¶39, 104).

Identified Points of Contention

  • Scope Questions: A central issue for both the '340 and '269 patents may be the scope of the terms "completely overlaps" and "substantially no overlap." The litigation will likely involve disputes over the degree of geometric alignment and the amount of metal overlap required to meet these limitations.
  • Technical Questions: For the '340 patent, a key question for the court will be whether the physical structures within the accused GPUs, as revealed through discovery or reverse engineering, actually contain cutouts that meet every limitation of the claims. For the '269 patent, the question will be evidentiary: what proof demonstrates that NVIDIA’s manufacturing process necessarily executes each step recited in the asserted method claims?

V. Key Claim Terms for Construction

Term: "cutout"

  • Context and Importance: This term defines the core inventive feature. Its construction will determine which physical voids or patterned areas in an accused device's metal layers can satisfy the claim limitation, making it central to the infringement analysis for the '340 and '269 patents.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims define the term functionally as being "for reducing parasitic capacitance," which may support an interpretation covering any void created for that purpose ('340 Patent, col. 10:52-56).
    • Evidence for a Narrower Interpretation: The '340 patent specification explains that the "cutout 508 encloses the cutout area 510 so that the area enclosed by the ball pad 108 is completely surrounded by the cutout area 510" ('340 Patent, col. 4:31-33). This language, tying the cutout to a structure that "surrounds" a pad, could support a narrower construction requiring a specific enclosing or encircling geometry.

Term: "completely overlaps"

  • Context and Importance: This term dictates the required spatial relationship between the insulating area created by the "cutout" and the underlying "contact pad". A slight misalignment in an accused product could be the difference between infringement and non-infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party might argue the term should be read in light of the claim's ultimate purpose of achieving "substantially no overlap" of metal with the contact pad, potentially allowing for minor geometric imperfections that do not frustrate this purpose ('340 Patent, col. 10:64-66).
    • Evidence for a Narrower Interpretation: The use of the strong modifier "completely" suggests a very high, if not absolute, standard of alignment. A defendant could argue this requires near-perfect coaxial alignment between the perimeter of the insulating area and the perimeter of the contact pad, as depicted in the patent's figures (e.g., '340 Patent, Fig. 5).

VI. Other Allegations

Indirect Infringement

The complaint focuses on direct infringement under 35 U.S.C. § 271(a) for all defendants (Compl. ¶64, 112, etc.). For defendants other than NVIDIA, the infringement is based on their making, using, selling, or importing products that incorporate the accused NVIDIA chips.

Willful Infringement

The complaint alleges willful infringement against all defendants for all asserted patents. The basis for willfulness against NVIDIA is alleged actual knowledge stemming from a series of pre-suit notice letters sent by Bell Semiconductor between March 2020 and June 2022, with specific dates provided for each patent (Compl. ¶67, 77, 87, 97, 107). The complaint alleges that infringement by the other defendants is also willful, based on their knowledge of the patents and the infringement contentions as of the filing of the complaint or original complaint in the action (Compl. ¶113, 123, 128, 133, etc.).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this multi-patent, multi-defendant lawsuit will likely depend on the court's findings on two central themes that cut across the various technologies at issue.

  • A core issue will be one of claim construction and scope: can the precise, geometric language of the patents—such as "completely overlaps" a contact pad ('340 patent), routing traces away from an area "within two ball pad pitches" of a die corner ('245 patent), or routing added trace length "entirely inside" a surrounding pad ('011 patent)—be met by the physical layouts of the accused high-density semiconductor products?
  • A second key issue will be one of evidentiary proof: for the apparatus claims, can the plaintiff demonstrate through complex reverse engineering that the internal, multi-layered structures of NVIDIA's chips contain every element as claimed? For the method claims ('269 patent), this question extends to whether discovery will yield evidence that NVIDIA’s proprietary manufacturing processes perform the recited steps.