DCT

2:24-cv-02864

Polaris PowerLED Tech LLC v. Western Digital Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:24-cv-02864, C.D. Cal., 06/21/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Central District of California based on Defendants' physical presence, regular transaction of business, and commission of infringing acts within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s solid-state drive (SSD) products infringe patents related to flash memory controller technology, specifically concerning interrupt management, adaptive error correction coding, and distributed parity data generation.
  • Technical Context: The lawsuit concerns foundational technologies for managing data and ensuring reliability in nonvolatile flash memory, which is a critical component in modern computing and data storage systems.
  • Key Procedural History: The complaint alleges that Defendant Western Digital was aware of U.S. Patent No. 8,554,968 because it was cited as prior art during the prosecution of several of Western Digital's own patents. Plaintiff also alleges sending a notice letter to Western Digital regarding infringement of the asserted patents on January 23, 2024.

Case Timeline

Date Event
2010-08-16 Priority Date for ’968 and ’346 Patents
2011-05-25 Priority Date for ’085 Patent
2013-10-08 U.S. Patent No. 8,554,968 Issues
2013-12-03 U.S. Patent No. 8,601,346 Issues
2015-11-10 U.S. Patent No. 9,183,085 Issues
2022-01-01 WD_BLACK SN770 NVMe SSD Launch Date
2024-01-23 Plaintiff sends notice letter to Western Digital
2024-06-21 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,554,968: "Interrupt Technique for a Nonvolatile Memory Controller" (issued Oct. 8, 2013)

The Invention Explained

  • Problem Addressed: The patent describes that conventional systems required a host computer's main processor (CPU) to continuously monitor memory controllers to see if read/write tasks were complete. This "polling" consumed significant CPU resources, cache memory, and communication bus bandwidth, which could bottleneck system performance (Compl. ¶39; ’968 Patent, col. 16:28-42).
  • The Patented Solution: The invention proposes a nonvolatile memory controller with its own "interrupt manager." Instead of the host CPU constantly checking for completed tasks, the memory controller’s interrupt manager determines when a task is finished, generates an "interrupt message packet," and sends it to the host CPU. This interrupt alerts the host CPU that there is a completed task ready for processing, freeing the CPU from the burden of constant monitoring (Compl. ¶37; ’968 Patent, col. 2:4-26).
  • Technical Importance: This architectural shift improves system efficiency and responsiveness by offloading a recurring, low-level monitoring task from the host CPU to the specialized memory controller hardware (Compl. ¶40).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶68).
  • Claim 1 recites a nonvolatile memory controller comprising:
    • An interrupt manager configured to generate a completion queue state indicating a completion queue event has occurred.
    • The interrupt manager is further configured to generate an interrupt vector state based on the completion queue state.
    • The interrupt manager is further configured to determine that the host's completion queue contains an unprocessed completion status based on the interrupt vector state.
    • The interrupt manager is further configured to generate an interrupt message packet to trigger an interrupt in the host to alert it of the unprocessed status.
    • The completion queue state includes a doorbell update status indicating the host has updated a head pointer in the memory controller.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,183,085: "Systems and Methods for Adaptively Selecting from among a Plurality of Error Correction Coding Schemes in a Flash Drive for Robustness and Low Latency" (issued Nov. 10, 2015)

The Invention Explained

  • Problem Addressed: Flash memory cells degrade over time, leading to higher bit error rates (BER). The patent notes that conventional systems used a single, static Error Correction Coding (ECC) scheme, which was inefficient. A scheme strong enough for an old, degraded memory cell was overkill for a new one, wasting storage space and processing time, while a weaker scheme might not provide enough protection as the drive aged ('085 Patent, col. 2:23-27; Compl. ¶46).
  • The Patented Solution: The invention describes a system that uses multiple, predefined ECC schemes, or "gears," each with a different balance of data payload size and correction capability. The controller determines the BER for a specific region of the flash memory and adaptively selects the appropriate gear for that region. As a region degrades, data can be migrated to a stronger gear with more error correction capability (at the cost of less user data space) to maintain reliability ('085 Patent, col. 4:37-49; Compl. ¶48).
  • Technical Importance: This adaptive approach extends the usable lifespan of flash memory devices and optimizes performance by applying only the necessary level of error correction, which allows for faster read/write operations and more efficient data storage when error rates are low (Compl. ¶¶51-52).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶89).
  • Claim 1 recites a method of selecting an ECC scheme, comprising:
    • Determining a bit error rate associated with a region of flash memory pages.
    • Comparing the determined bit error rate to predetermined thresholds corresponding to a set of predefined "gears."
    • The gears correspond to different ECC schemes, with a first gear having a different data payload size and correction capability than a second gear.
    • The amount of memory space for data payload within the region varies between the gears to accommodate a varying number of parity symbols.
    • Selecting a gear from the set based on the comparisons.
    • The determining, comparing, and selecting steps are performed by an integrated circuit.
  • The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsule: U.S. Patent No. 8,601,346: "System and Method for Generating Parity Data in a Nonvolatile Memory Controller by Using a Distributed Processing Technique" (issued Dec. 3, 2013)

  • Technology Synopsis: The patent addresses the performance bottleneck of generating parity data for RAID (Redundant Array of Independent Disks) operations in conventional controllers, which required a dedicated processor and large data buffers ('346 Patent, col. 1:40-46; Compl. ¶59). The patented solution employs a distributed architecture with multiple command processing units working in parallel and a parity calculator that generates the parity block "on the fly" as data blocks arrive, eliminating the need to buffer all data blocks of a stripe simultaneously. This is alleged to reduce power consumption, silicon area, and latency (Compl. ¶¶61-62, 64; '346 Patent, col. 2:4-17).
  • Asserted Claims: At least independent claim 1 (Compl. ¶111).
  • Accused Features: The complaint alleges that Defendants' SSD controllers, which feature multi-core architectures (command processing units) and hardware engines for LDPC and RAID-like schemes (parity calculator), infringe the ’346 Patent by performing data stripe operations (Compl. ¶¶114, 115, 118).

III. The Accused Instrumentality

  • Product Identification: The accused products are Defendants' solid-state drives (SSDs) and their constituent nonvolatile memory controllers (NVMCs). The complaint names specific product lines, including WD Black, Blue, Green, Red, Gold, and Ultrastar SSDs (Compl. ¶¶17, 71, 92). A product photo of the WD_BLACK SN770 NVMe SSD is provided as an exemplary accused product (Compl. p. 20).
  • Functionality and Market Context: The accused products are high-performance flash memory storage devices that support the NVMe (Non-Volatile Memory Express) industry standard for communicating with a host system over a PCIe interface (Compl. ¶71). The complaint alleges these SSDs are used in a wide range of applications, from consumer gaming PCs and consoles to enterprise data centers and Network Attached Storage (NAS) systems (Compl. ¶¶71, 92). The complaint includes a diagram contrasting the higher performance of the NVMe interface with the older SATA standard to illustrate its market importance (Compl. p. 20, "NVMe vs. SATA"). The core accused functionality resides in the SSDs' internal controllers, which are alleged to manage host interrupts, perform adaptive multi-gear error correction, and use multiple processing cores to execute distributed data striping operations (Compl. ¶¶74, 92, 115).

IV. Analysis of Infringement Allegations

’968 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an interrupt manager configured to generate a completion queue state for indicating the occurrence of a completion queue event associated with the completion queue... The accused SSDs' controller, compliant with the NVMe standard, generates a completion queue entry after a command completes, which constitutes a "completion queue event." A diagram shows this as step 5 in the command processing flow (Compl. p. 22). ¶74 col. 2:4-26
generate an interrupt vector state based on the completion queue state... The NVMe standard specifies that an Interrupt Vector field is used for the completion queue, corresponding to an MSI-X vector. This vector is the basis for generating an interrupt. A figure from the NVMe specification shows this "Interrupt Vector (IV)" field (Compl. p. 23). ¶75 col. 2:13-17
determine the completion queue of the host processing unit contains an unprocessed completion status based on the interrupt vector state, and generate an interrupt message packet for triggering an interrupt... The NVMe controller "optionally generates an interrupt to the host to indicate that there is a new completion queue entry to consume and process." This interrupt is generated as an MSI-X interrupt, which is transmitted as a PCIe message packet. A command processing diagram illustrates this interrupt generation at step 6 (Compl. p. 24). ¶76-77 col. 2:20-26
wherein the completion queue state includes a doorbell update status indicating whether the host processing unit has performed a doorbell update event in which the host processing unit updates a head pointer stored in the nonvolatile memory controller... The NVMe process requires the host to write to a "Completion Queue Head Doorbell register" to indicate it has consumed an entry. This action constitutes the claimed doorbell update event and updates the head pointer. This is shown as step 8 in the command processing flow diagram (Compl. p. 25). ¶78 col. 17:1-12
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the term "interrupt manager" as claimed in the patent is coextensive with the standardized interrupt mechanism of the NVMe protocol. Defendants may argue the patent claims a specific implementation or architecture not required by the standard, while Plaintiff's theory appears to equate compliance with the NVMe standard to infringement.
    • Technical Questions: The dispute may focus on whether the standard NVMe process, as implemented in the accused products, includes every specific function attributed to the "interrupt manager" in Claim 1, such as generating a distinct "completion queue state" and "interrupt vector state" that map to specific structures in the patent's embodiments (e.g., '968 Patent, Fig. 11-13).

’085 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
determining a bit error rate associated with a region comprising a fixed number of two or more flash memory pages... The accused products' "Sentinel ECC&DSP LDPC decoder" is described in a white paper as optimizing power "under variable BER observed across memory pages," which the complaint alleges is the claimed determination step. ¶93 col. 4:37-41
comparing the determined bit error rate to one or more predetermined thresholds corresponding to a set of predefined gears... A Western Digital document shows a graph of "various decoding gears correction capability" versus BER, illustrating that as BER increases, the system transitions from "Gear 1" to "Gear 2" and "Gear 3," which corresponds to comparing the BER to thresholds. ¶96 col. 4:41-43
wherein the predefined gears correspond to different predefined ECC schemes, wherein the first gear has a different data payload size and correction capability than the second gear... An architectural diagram titled "Western Digital ECC Architecture" explicitly shows "Gear 1" providing "High Throughput," while "Gear 2 and 3" provide "Stronger correction capabilities." The complaint alleges this corresponds to different correction capabilities and, consequently, different payload sizes. ¶97 col. 4:43-46
selecting a gear from the set for the region based at least partly on the comparisons... A Western Digital white paper is quoted stating its LDPC engine "estimates the BER of the noisy page...This forms the basis on which it automatically chooses the appropriate decoding gear." ¶99 col. 4:47-49
  • Identified Points of Contention:
    • Scope Questions: The case may turn on the construction of "predefined gears." Defendants might argue their "multi-gear LDPC" system, while using the same terminology, operates differently from what is claimed—for example, by adjusting decoder iterations or power rather than explicitly varying the "amount of memory space allocated for the storage of data payload" as required by the claim.
    • Technical Questions: An evidentiary question may be whether the accused products actually vary the data payload size between gears. While stronger correction (more parity bits) implies less space for data payload, the complaint relies on marketing and high-level technical documents. The actual implementation will be a focus of discovery.

V. Key Claim Terms for Construction

’968 Patent, Claim 1: "interrupt manager"

  • Context and Importance: This term is the central component of the invention. The infringement case rests on whether the accused products' NVMe-compliant interrupt functionality constitutes the claimed "interrupt manager." Its construction will likely determine the outcome of infringement for this patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's summary describes the interrupt manager in functional terms, stating it is "configured to determine a completion queue...contains an unprocessed completion status" and "generate an interrupt message packet" ('968 Patent, col. 1:59-63). Plaintiff may argue that any hardware module performing these functions, regardless of its specific internal design, falls within the claim's scope.
    • Evidence for a Narrower Interpretation: The detailed description discloses a specific architecture for the "Interrupt Manager 1040," which includes an "Interrupt Manager Controller 1100," a "Completion Queue State Memory 1105," and an "Interrupt Vector State Memory 1110" ('968 Patent, Fig. 11). Defendants may argue the term should be limited to this or a structurally similar arrangement, potentially excluding a standard NVMe implementation if it lacks these specific, separate components.

’085 Patent, Claim 1: "wherein the amount of memory space allocated for the storage of data payload within the region varies between the first gear and the second gear to accommodate a varying number of parity symbols"

  • Context and Importance: This clause specifies how the "gears" must differ. It is not enough for them to simply have different ECC schemes; the claim requires a specific structural change in data allocation. Practitioners may focus on this term because it presents a specific, falsifiable technical requirement for infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Plaintiff may argue that this is an inherent and necessary consequence of changing ECC strength. A stronger ECC scheme (more correction capability) requires more parity symbols, which necessarily leaves less memory space for the data payload within a fixed-size page. The claim language could be interpreted as describing this functional outcome rather than a specific mechanism.
    • Evidence for a Narrower Interpretation: Defendants may argue this clause requires an explicit, active step of "varying" the allocated space, rather than it being a passive consequence of selecting a different code. They could contend their system uses fixed payload and parity block sizes and achieves different correction strengths through other means (e.g., different decoding algorithms or iteration counts) not covered by the claim. The specification does not appear to elaborate extensively on the mechanism for varying the space, which may leave the term open to interpretation based on its plain meaning.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents. Inducement is based on allegations that Defendants intentionally instruct customers to use the infringing features of the SSDs through user guides, product briefs, support websites, and marketing videos (Compl. ¶¶80-81, 104-105, 129-130). Contributory infringement is based on allegations that the SSDs are material components specifically adapted for infringing use and are not staple articles of commerce suitable for substantial noninfringing use (Compl. ¶¶85, 106, 131).
  • Willful Infringement: Willfulness is alleged based on both pre- and post-suit knowledge. Pre-suit knowledge of the ’968 Patent is alleged based on Western Digital having cited it as prior art during the prosecution of its own patents (Compl. ¶82). Pre-suit knowledge for all asserted patents is also alleged based on a notice letter sent by Plaintiff on January 23, 2024 (Compl. ¶¶83, 102, 127). The complaint alleges that continued infringement after receiving this notice is willful.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of invention versus standardization: for the ’968 patent, can practicing the industry-standard NVMe interrupt protocol constitute infringement of a patented "interrupt manager," or does the patent claim a specific architecture that the standard does not mandate? The answer will depend on how broadly the court construes the claims in light of the patent's specification.
  • A key evidentiary question will be one of technical implementation: for the ’085 patent, does the accused "multi-gear" ECC system operate by varying the allocated memory space for data payload as the claim requires, or does it achieve different correction levels through other technical means? This will likely require deep discovery into the design and operation of the accused memory controllers.
  • A central question for damages will be knowledge and willfulness: the complaint's allegation that Western Digital previously cited the ’968 patent as prior art presents a specific factual basis for pre-suit knowledge that could significantly influence a finding of willfulness if infringement is found.