DCT

8:15-cv-00278

Limestone Memory Systems LLC v. Micron Technology Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: Limestone Memory Systems LLC v. Micron Technology, Inc., 8:15-cv-00278, C.D. Cal., 02/17/2015
  • Venue Allegations: Venue is alleged to be proper based on Defendants' business operations, sales, and commission of infringing acts within the Central District of California, with specific corporate facilities for several defendants being located within the district.
  • Core Dispute: Plaintiff alleges that semiconductor memory components (DRAM and Flash chips) manufactured by Micron and incorporated into end-products by other defendants infringe three patents related to memory device architecture, redundancy, and programming methods.
  • Technical Context: The lawsuit concerns foundational technologies in synchronous dynamic random-access memory (DRAM) and non-volatile flash memory, which are critical components for data storage and processing in a vast range of electronic devices from consumer laptops to enterprise servers.
  • Key Procedural History: The complaint details the chain of title for the patents-in-suit, originating with NEC Corporation and assigned to Plaintiff Limestone Memory Systems LLC via Renesas and Acacia Research Group LLC. Subsequent to the complaint's filing, all claims of U.S. Patent No. 5,943,260 were cancelled in an Inter Partes Review (IPR2016-00095). Additionally, a disclaimer was filed for U.S. Patent No. 5,894,441, disclaiming claims 1-3 and 5, which may substantially impact the scope of the infringement case for that patent.

Case Timeline

Date Event
1995-11-29 U.S. Patent 5,805,504 Priority Date
1997-02-21 U.S. Patent 5,943,260 Priority Date
1997-03-31 U.S. Patent 5,894,441 Priority Date
1998-09-08 U.S. Patent 5,805,504 Issue Date
1999-04-13 U.S. Patent 5,894,441 Issue Date
1999-08-24 U.S. Patent 5,943,260 Issue Date
2015-02-17 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,805,504 - "Synchronous Semiconductor Memory Having A Burst Transfer Mode With A Plurality Of Subarrays Accessible In Parallel Via An Input Buffer"

  • Patent Identification: U.S. Patent No. 5,805,504, "Synchronous Semiconductor Memory Having A Burst Transfer Mode With A Plurality Of Subarrays Accessible In Parallel Via An Input Buffer," issued September 8, 1998 (Compl. ¶24).

The Invention Explained

  • Problem Addressed: The patent’s background describes the speed disparity between high-speed CPUs and comparatively slower DRAM main memory, which creates a system bottleneck (’504 Patent, col. 1:11-23). Conventional methods to speed up DRAM data transfer, such as pipelining and prefetching, are described as having inherent limitations, including circuit overhead and a dependency on internal address processing that can slow write operations (’504 Patent, col. 5:1-35).
  • The Patented Solution: The invention proposes a synchronous DRAM architecture with an improved input buffer to accelerate data writing. The buffer uses a shift register, composed of cascade-connected registers, to receive serial data from an external bus and convert it into parallel data (’504 Patent, Abstract; col. 9:31-53). A register output selector then distributes this parallel data to a plurality of internal data buses, which write to memory sub-arrays simultaneously. This design aims to decouple the external data reception from the internal write execution, enabling what the patent calls an "asynchronous pipelined writing process" (’504 Patent, col. 12:13-25).
  • Technical Importance: This architecture was designed to increase the maximum burst transfer frequency of DRAM, allowing memory to better match the performance of contemporary high-speed processors while avoiding some of the scaling and flexibility issues of prior art solutions (’504 Patent, col. 12:55-59).

Key Claims at a Glance

  • The complaint does not identify specific claims asserted against the Defendants. The first independent claim of the patent is Claim 1.
  • Essential elements of Independent Claim 1 include:
    • A plurality of memory cell sub-arrays accessible in parallel.
    • A plurality of internal data buses for parallel data input/output to the sub-arrays.
    • An input buffer circuit that converts received serial data to parallel data for distribution to the internal data buses.
    • The input buffer circuit includes a specific structure: a "shift register circuit composed of a plurality of cascade-connected registers" and a "register output selecting means" for distributing the data in accordance with an external address signal.

U.S. Patent No. 5,894,441 - "Semiconductor Memory Device With Redundancy Circuit"

  • Patent Identification: U.S. Patent No. 5,894,441, "Semiconductor Memory Device With Redundancy Circuit," issued April 13, 1999 (Compl. ¶59).

The Invention Explained

  • Problem Addressed: The patent addresses the inefficiency of conventional redundancy circuits in semiconductor memories. When a single bit line in a column is defective, prior art methods often require replacing the entire column selection line, thereby disabling numerous otherwise functional bit lines and wasting valuable redundant resources (’441 Patent, col. 3:56-4:5).
  • The Patented Solution: The invention describes a "row flexible redundancy" method where the column redundancy decoder uses not only the column address but also a portion of the row address to identify a defect. This allows the system to replace only a specific, defective segment of a column line, rather than the entire line (’441 Patent, Abstract; col. 2:13-28). The replacement is triggered only when both the column and the relevant part of the row address match the location of a known defect (’441 Patent, Fig. 3).
  • Technical Importance: This technique significantly improves the "relief efficiency" for defective bit lines, allowing manufacturers to repair more defects with fewer redundant circuits, thereby increasing production yields and reducing costs (’441 Patent, col. 7:41-48).

Key Claims at a Glance

  • The complaint does not identify specific claims asserted. Notably, a post-complaint disclaimer cancelled independent Claim 1, which explicitly recited using "at least a part of a row address" in the redundancy decision. The first surviving independent claim is Claim 4.
  • Essential elements of Independent Claim 4 include:
    • A memory architecture with word lines, bit lines, and memory cells.
    • A plurality of column selection lines.
    • A redundant column selection line.
    • A column decoder for activating a column selection line.
    • A "column redundancy decoder" that performs its function such that it "inactivates none of said plurality of column selection lines when said redundant column selection line is activated."

U.S. Patent No. 5,943,260 - "Method For High-Speed Programming Of A Nonvolatile Semiconductor Memory Device"

  • Patent Identification: U.S. Patent No. 5,943,260, "Method For High-Speed Programming Of A Nonvolatile Semiconductor Memory Device," issued August 24, 1999 (Compl. ¶94).
  • Technology Synopsis: This patent describes a method to accelerate the programming of multi-level cell (MLC) non-volatile memories, such as flash memory. The problem is that programming cells to different voltage levels in parallel can be slow. The patented solution involves a multi-step process where all cells in a programming group are first written to a common intermediate voltage level, and then specific subgroups are incrementally programmed to their final, higher voltage levels, reducing overall programming time and improving reliability (’260 Patent, Abstract; col. 3:9-30).
  • Asserted Claims: The complaint does not specify asserted claims. However, all claims of the patent (Claims 1-5) were subsequently cancelled as a result of an Inter Partes Review proceeding (IPR2016-00095).
  • Accused Features: The complaint accuses Micron’s flash memory chips that incorporate "multi-level cell ('MLC') and triple-level cell ('TLC') technology" and the end-products that contain them (Compl. ¶¶ 96, 117, 122).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are broadly defined as memory devices and products incorporating them. They fall into two main categories:

  1. DRAM Products: Micron's DDR2, DDR3, and DDR4 DRAM chips, which are alleged to infringe the '504 and '441 patents. Downstream products include servers, personal computers, and laptops from defendants like Dell, HP, and Lenovo (Compl. ¶¶ 26, 32, 37, 42).
  2. Flash Memory Products: Micron's flash memory chips featuring MLC and TLC technology, which are alleged to infringe the '260 patent. Downstream products include solid-state drives (SSDs), USB flash drives, and computers from defendants like OCZ, PNY, and Transcend (Compl. ¶¶ 96, 102, 117, 122).

Functionality and Market Context

The complaint alleges that Micron is a primary manufacturer of these memory components, which are then incorporated into a wide array of electronic devices sold by the other defendants (Compl. ¶¶ 57, 92). The core allegation is that these components contain circuitry and operate in a manner that practices the inventions claimed in the patents-in-suit (Compl. ¶¶ 26, 61, 96). The complaint identifies specific product lines, such as Dell's XPS13 laptops, HP's Integrity Servers, and OCZ's Arc 100 Series SSDs, as exemplary infringing devices (Compl. ¶¶ 32, 37, 47).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

5,805,504 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of memory cell sub-arrays which are accessible in parallel and simultaneously; Micron’s DDR2, DDR3, and DDR4 DRAM Chips are alleged to embody the patented inventions; such memory is architected with multiple banks or sub-arrays to facilitate parallel data access. ¶26 col. 7:40-49
a plurality of internal data buses for inputting and outputting data to and from said plurality of memory cell sub-arrays, in parallel; The accused DRAM chips are alleged to use multiple internal data buses to transfer data between the memory core and I/O circuits in a parallel fashion. ¶26 col. 7:56-61
an input buffer circuit receiving an external data signals continuously and sequentially in time in synchronism with a reference clock signal, for converting said receiving serial data into a parallel data... so as to distribute said parallel data to said plurality of internal data buses, The complaint alleges the accused DRAM chips perform this function. Synchronous DRAM standards like DDR require receiving serial data bursts and converting them for internal parallel processing. ¶26 col. 9:20-29
the input buffer circuit including a shift register circuit composed of a plurality of cascade-connected registers... and a register output selecting means... for distributing said received parallel data signals... in accordance with said external address signal. The complaint alleges the accused chips embody this specific claimed structure for converting serial data to parallel data and distributing it to internal buses. ¶26 col. 9:40-10:17
  • Identified Points of Contention:
    • Technical Questions: A central question will be whether the input buffer circuits in Micron’s accused DRAM chips actually contain the specific structure of a "shift register circuit composed of a plurality of cascade-connected registers" as claimed. While the chips perform a serial-to-parallel conversion, the court will need to determine if the implementation is structurally equivalent to the one claimed, or if it represents a distinct, non-infringing design.
    • Scope Questions: The dispute may focus on the scope of "register output selecting means." Does the accused circuitry for routing data from the input buffer to the internal data buses operate "in accordance with the external address signal" in the manner required by the claim and described in the patent specification?

5,894,441 Patent Infringement Allegations

Claim Element (from Independent Claim 4) Alleged Infringing Functionality Complaint Citation Patent Citation
a plurality of word lines; a plurality of bit lines; a plurality of memory cells... a plurality of column selection lines... a redundant column selection line... a column decoder activating said first column selection line... The accused Micron DRAM chips are alleged to contain these standard memory components and redundancy structures. ¶61 col. 3:1-15
a column redundancy decoder inactivates none of said plurality of column selection lines when said redundant column selection line is activated. The complaint's allegation of infringement implies that the accused chips' redundancy system meets this negative limitation, suggesting a partial replacement mechanism that leaves the main column line active. ¶61 col. 5:16-24
  • Identified Points of Contention:
    • Scope Questions: A critical issue arises from the disclaimer of Claim 1, which explicitly recited the use of a row address in the column redundancy decision. The key question for the court will be whether the term "column redundancy decoder" in the surviving Claim 4 should be interpreted in light of the specification to include the "row flexible" functionality, or if the disclaimer limits the claim to its plain language, potentially excising the core inventive concept from its scope.
    • Technical Questions: Factually, does the redundancy mechanism in the accused Micron chips operate as required by Claim 4? Specifically, when a redundant line is activated to repair a defect, does the primary column selection line remain active, and is the selection between the main and redundant paths managed in a way that meets the claim limitations?

V. Key Claim Terms for Construction

For the '504 Patent:

  • The Term: "shift register circuit composed of a plurality of cascade-connected registers"
  • Context and Importance: This term defines the core structure of the claimed input buffer. The infringement analysis will depend heavily on whether the architecture of the input buffers in Micron's DRAMs falls within the scope of this term. Practitioners may focus on this term because modern high-speed DRAMs employ highly complex input-output circuitry, and any structural deviation from the patent's specific embodiment could form the basis of a non-infringement defense.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the purpose of the circuit is to convert serial data to parallel data to enable an "asynchronous pipelined writing process" (’504 Patent, col. 12:13-25). A party might argue the term should be construed functionally to cover different circuit designs that achieve this same cascaded latch-and-shift result.
    • Evidence for a Narrower Interpretation: The patent depicts a specific embodiment in Figure 5 showing two registers (REGO, REG1) where the output of the first directly feeds the input of the second (’504 Patent, col. 9:40-53). A party could argue the term should be limited to this direct, sequential cascade structure, as opposed to other forms of parallel-load or differently clocked registers.

For the '441 Patent:

  • The Term: "column redundancy decoder"
  • Context and Importance: The definition of this term is central to the case, especially following the disclaimer of Claim 1. The patent's invention is a "row flexible" redundancy scheme, a feature tied directly to how the "column redundancy decoder" operates. Whether this feature can be read into the surviving claims will be a dispositive issue.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The abstract and detailed description repeatedly frame the invention as a column redundancy decoder that is responsive to a portion of the row address (’441 Patent, Abstract; col. 2:13-28). A party may argue that to give the patent meaning, the term "column redundancy decoder" must be construed to be one that performs this novel function.
    • Evidence for a Narrower Interpretation: The express recitation of using a "part of a row address" appeared in Claim 1 but is absent from Claim 4. The subsequent disclaimer of Claim 1 provides strong prosecution history evidence that the patentee surrendered coverage for this specific feature in the remaining claims, suggesting "column redundancy decoder" should be given its plain meaning without the "row flexible" limitation.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges contributory infringement against Micron, asserting that its DRAM and Flash chips are material components especially made or adapted for infringing the patents and are not staple articles of commerce with substantial non-infringing uses (Compl. ¶¶ 27-28, 62-63, 97-98). The complaint also alleges that all defendants enable end-users to use the infringing devices, which could form a basis for an inducement theory (Compl. ¶¶ 19-20).
  • Willful Infringement: Willfulness allegations are based on knowledge gained from the service of the complaint itself. The complaint asserts that any continued infringement by the defendants after receiving notice of the lawsuit will be willful, as they will lack an objectively reasonable basis to believe their activities are non-infringing (Compl. ¶¶ 31, 41, 66). No facts supporting pre-suit knowledge are alleged.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of patent viability: Following the cancellation of all claims of the '260 patent and the disclaimer of the central "row flexible" limitation from Claim 1 of the '441 patent, what is the enforceable scope, if any, of the remaining asserted claims? The court's treatment of the '441 patent's prosecution history will be particularly consequential.
  • A key infringement question will be one of structural correspondence: For the '504 patent, does the input buffer circuitry in Micron's high-performance DRAMs utilize the specific "shift register circuit" architecture recited in Claim 1, or does it achieve a similar functional outcome through a materially different and non-infringing design?
  • A central procedural question will be one of liability and joinder: The case joins a component supplier (Micron) with numerous downstream original equipment manufacturers (OEMs). Resolving whether this joinder is proper and how liability for direct and indirect infringement should be apportioned between the chipmaker and the system integrators will be a critical aspect of the litigation.