DCT
8:16-cv-02055
North Star Innovations Inc v. Integrated Device Technology Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: North Star Innovations Inc. (Delaware)
- Defendant: Integrated Device Technology, Inc. (Delaware)
- Plaintiff’s Counsel: SHK Legal, APC; Whitaker Chalk Swindle & Schwartz PLLC
- Case Identification: 8:16-cv-02055, C.D. Cal., 11/14/2016
- Venue Allegations: Plaintiff alleges venue is proper in the Central District of California because Defendant conducts regular business in the state and district, and has allegedly made, used, sold, or imported the accused products within the district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including certain Synchronous Dual-Port SRAM and DDR4 Register devices, infringe three patents related to semiconductor memory architecture, microelectronic packaging, and manufacturing methods.
- Technical Context: The technologies at issue involve the fundamental design and manufacturing of integrated circuits, specifically relating to high-speed memory access and the physical packaging and assembly of semiconductor dies.
- Key Procedural History: The complaint notes that Plaintiff is actively engaged in licensing efforts concerning its patent portfolio. Post-dating the complaint, U.S. Patent No. 6,465,743, one of the patents-in-suit, was the subject of an Inter Partes Review (IPR2018-01000). The proceeding resulted in the cancellation of all claims of the '743 patent, which may substantially impact the third count of the complaint.
Case Timeline
| Date | Event |
|---|---|
| 1994-12-05 | Priority Date for U.S. Patent No. 6,465,743 |
| 1997-05-19 | Priority Date for U.S. Patent No. 6,093,972 |
| 1997-07-29 | Priority Date for U.S. Patent No. 5,781,480 |
| 1998-07-14 | U.S. Patent No. 5,781,480 Issued |
| 2000-07-25 | U.S. Patent No. 6,093,972 Issued |
| 2002-10-15 | U.S. Patent No. 6,465,743 Issued |
| 2016-11-14 | Complaint Filed |
| 2018-05-01 | Inter Partes Review (IPR2018-01000) Filed for U.S. Patent No. 6,465,743 |
| 2022-12-16 | IPR Certificate Issued Cancelling All Claims of U.S. Patent No. 6,465,743 |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 5,781,480 - “Pipelined Dual Port Integrated Circuit Memory” (’480 Patent)
The Invention Explained
- Problem Addressed: The patent’s background describes a need for dual-port memories that are large, fast, and inexpensive for use in applications like communications routers and multiprocessor systems. Conventional approaches were either too expensive and large (using eight-transistor memory cells) or were subject to access delays and collisions (using partitioned memory arrays) (ʼ480 Patent, col. 1:10-38).
- The Patented Solution: The invention proposes a memory architecture that provides dual-port functionality using a standard, more compact single-port Static Random Access Memory (SRAM) array. This is achieved by operating the internal memory core at twice the speed of the external clock, allowing a control circuit to service two separate access requests (one for each "port") sequentially within a single external clock cycle (’480 Patent, Abstract; col. 2:62-65). This design aims to simulate dual-port performance while retaining the cost and density benefits of single-port SRAM cells (’480 Patent, col. 4:51-59).
- Technical Importance: This architecture offered a method to achieve the high-throughput benefits of dual-port memory, which is critical for systems handling simultaneous data streams, without incurring the significant die-size and cost penalties associated with true dual-port memory cells (ʼ480 Patent, col. 1:10-23).
Key Claims at a Glance
- The complaint asserts independent Claim 1 (Compl. ¶18).
- Essential elements of Claim 1 include:
- A plurality of memory cells, each coupled to a single word line and a single bit line pair.
- An address decoder for selecting a memory cell.
- A first address port and a second address port for providing separate addresses.
- A read data port and a write data port for accessing the memory cells.
- A control circuit that controls access, wherein "substantially simultaneous requests for access...are serviced sequentially within a single clock cycle of a clock signal of a data processor."
- The complaint reserves the right to assert additional claims (Compl. ¶21).
U.S. Patent No. 6,093,972 - “Microelectronic Package Including a Polymer Encapsulated Die” (’972 Patent)
The Invention Explained
- Problem Addressed: The patent identifies a need to improve the reliability of microelectronic packages that use solder bumps to connect a semiconductor die to a substrate. These solder bumps require mechanical reinforcement, and the exposed back side of the die needs protection from environmental degradation and physical damage. Accomplishing both could involve multiple, complex manufacturing steps (’972 Patent, col. 1:35-62).
- The Patented Solution: The invention describes a packaging structure and method where a die is attached to a substrate and then "overmolded." A mold is placed over the assembly, and a liquid polymer is injected. This polymer not only forms a protective layer over the back of the die but also flows into the gap between the die and the substrate to encapsulate and reinforce the solder bumps. This single-step process provides both reinforcement and backside protection (’972 Patent, Abstract; col. 2:22-44).
- Technical Importance: This method simplifies the manufacturing process by combining underfill (for solder bump reinforcement) and overmolding (for backside protection) into a single, efficient operation suitable for mass production on large panels containing multiple dies (’972 Patent, col. 4:17-26).
Key Claims at a Glance
- The complaint asserts independent Claim 1 (Compl. ¶25).
- Essential elements of Claim 1 include:
- A carrier substrate with a die attach region and surrounding region.
- An integrated circuit die overlying the die attach region, separated by a gap, with an active face and a back face.
- A plurality of solder bump interconnections extending across the gap.
- An "encapsulant formed of a singular polymeric body" that overlies the die's back face and is molded against the surrounding region, with the encapsulant body having "sides coextensive with said carrier sides."
- The complaint reserves the right to assert additional claims (Compl. ¶27).
U.S. Patent No. 6,465,743 - “Multi-Strand Substrate for Ball-Grid Array Assemblies and Method” (’743 Patent)
Technology Synopsis
The patent describes a method for manufacturing Ball-Grid Array (BGA) packages. The technical problem addressed is that thin BGA substrates tend to warp during assembly, requiring the use of costly support pallets in automated manufacturing lines (’743 Patent, col. 1:36-55). The patented method uses a thicker, more rigid printed circuit board arranged in a multi-row, multi-column ("N by M") array, which is stable enough to proceed through automated assembly without pallets, thereby increasing throughput and reducing cost (’743 Patent, Abstract).
Asserted Claims
The complaint asserts independent method Claim 1 (Compl. ¶31).
Accused Features
The complaint alleges infringement under 35 U.S.C. § 271(g), stating that Defendant's "IDT SRAM" products are imported into the U.S. after being manufactured abroad using the patented method (Compl. ¶31-¶32).
III. The Accused Instrumentality
Product Identification
The complaint identifies two specific product lines:
- IDT SRAM: A "128Kx36 Synchronous Dual-Port SRAM, IDT Part No. IDT70V3599," accused of infringing the ’480 Patent and of being made by the process of the ’743 Patent (Compl. ¶19, ¶32).
- DDR4 Register: An "IDT DDR4 Register, IDT Part No. 4RCD0124KC0ATG," accused of infringing the ’972 Patent (Compl. ¶25).
Functionality and Market Context
- The accused products are semiconductor components used in communications, computing, and other electronics segments (Compl. ¶3). The IDT SRAM is a memory chip alleged to provide dual-port functionality (Compl. ¶19). The DDR4 Register is a component used in modern computer memory modules (Compl. ¶25).
- The complaint alleges these and other unidentified products with "substantially similar circuitry" or structure also infringe the respective patents (Compl. ¶21, ¶27).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’480 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a plurality of memory cells, each of the plurality of memory cells being coupled to a single word line and to a single bit line pair | The complaint alleges the IDT SRAM contains a plurality of memory cells with the claimed single word line and single bit line pair structure. | ¶19-¶20 | col. 3:11-24 |
| an address decoder, coupled to the plurality of memory cells, for selecting a memory cell...in response to receiving an address | The complaint alleges the IDT SRAM contains an address decoder coupled to the memory cells for selecting a cell based on a received address. | ¶19-¶20 | col. 4:11-28 |
| a first address port...for providing a first address...; a second address port...for providing a second address | The complaint alleges the IDT SRAM contains first and second address ports for providing two addresses to the address decoder. | ¶19-¶20 | col. 2:15-18 |
| a read data port...for reading data...; a write data port...for writing data | The complaint alleges the IDT SRAM contains read and write data ports for accessing data in the memory cells. | ¶19-¶20 | col. 2:6-11 |
| a control circuit...wherein substantially simultaneous requests for access to the plurality of memory cells are serviced sequentially within a single clock cycle of a clock signal of a data processor | The complaint alleges the IDT SRAM contains a control circuit that services substantially simultaneous access requests sequentially within a single clock cycle. | ¶19-¶20 | col. 2:62-65 |
- Identified Points of Contention:
- Technical Question: The complaint’s allegations are conclusory and lack specific technical evidence. The central factual question will be whether the accused IDT SRAM actually operates by using a single-port memory core that is accessed twice per external clock cycle to simulate dual-port access, as required by the claim’s functional language. An alternative architecture, such as one using a true dual-port cell, would raise a significant non-infringement argument.
- Scope Question: A key issue for claim construction may be the meaning of "serviced sequentially within a single clock cycle of a data processor." The parties may dispute the specific timing and series of operations required to meet this limitation and whether the accused product's internal clocking scheme falls within that scope.
’972 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a carrier substrate that includes a die attachment face and carrier sides about the die attachment face, said die attachment face comprising a die attach region and a surrounding region about the die attach region | The complaint alleges the DDR4 Register package includes a carrier substrate with the claimed regions. | ¶25-¶26 | col. 3:1-4 |
| an integrated circuit die overlying the die attach region and spaced apart therefrom by a gap, said integrated circuit die including an active face facing the die attach region and a back face opposite the active face | The complaint alleges the DDR4 Register package includes an integrated circuit die situated over the substrate and separated by a gap as claimed. | ¶25-¶26 | col. 3:28-34 |
| a plurality of solder bump interconnections that extend across the gap and connect the integrated circuit die to the die attach region | The complaint alleges the DDR4 Register package uses solder bump interconnections that cross the gap to connect the die and substrate. | ¶25-¶26 | col. 3:31-34 |
| an encapsulant formed of a singular polymeric body overlying the back face and molded against the surrounding region so as to encapsulate the die therein, said body comprising sides coextensive with said carrier sides | The complaint alleges the DDR4 Register package has an encapsulant made of a single polymeric body that covers the die's back face and has sides aligned with the substrate's sides. | ¶25-¶26 | col. 4:21-26 |
- Identified Points of Contention:
- Technical Question: The infringement analysis will depend on the physical construction of the accused DDR4 Register. A determinative question is whether its encapsulant is, in fact, a single molded body that also serves as the underfill, or if it is constructed using separate overmold and underfill materials or processes.
- Scope Question: The limitation "sides coextensive with said carrier sides" suggests a specific final package geometry. A likely point of dispute will be whether this requires perfect vertical alignment between the encapsulant and substrate edges, or if it permits manufacturing tolerances. The method used to singulate (separate) the packages could be critical to this analysis.
V. Key Claim Terms for Construction
’480 Patent
- The Term: "substantially simultaneous requests for access ... are serviced sequentially within a single clock cycle"
- Context and Importance: This functional language is the core of the asserted claim, defining how the memory mimics dual-port behavior. The interpretation of "substantially simultaneous" and the precise timing of "serviced sequentially" will be dispositive for infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states that "there are no circumstances in which two accesses cannot occur within a single CLOCK cycle" (’480 Patent, col. 2:55-58), suggesting the term should be read broadly to cover any implementation that achieves this functional outcome.
- Evidence for a Narrower Interpretation: The detailed embodiment and timing diagrams (e.g., Fig. 6) illustrate a specific two-phase process where one port is serviced during the first half of a clock cycle and the second port during the second half (’480 Patent, col. 10:12-21). A party could argue the claim is limited to this specific implementation.
’972 Patent
- The Term: "sides coextensive with said carrier sides"
- Context and Importance: This structural limitation defines the final physical form of the package. Practitioners may focus on this term because it links the claim to a specific manufacturing outcome, likely a result of singulating a larger panel of devices by cutting through both the encapsulant and substrate at once.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party might argue "coextensive" allows for minor, commercially acceptable variations in alignment resulting from the manufacturing and cutting process.
- Evidence for a Narrower Interpretation: The description of singulation states that cutting the panel forms "encapsulant sides 46...coextensive with carrier sides 48" (’972 Patent, col. 4:35-39). This, along with Figure 4, suggests a requirement for a clean, flush vertical edge profile on the final package, which might not be present in all package types.
VI. Other Allegations
- Indirect Infringement: The complaint does not contain specific factual allegations to support claims for induced or contributory infringement. The infringement counts are for direct infringement (§271(a)) and importation of a product made by a patented process (§271(g)).
- Willful Infringement: The complaint does not use the term "willful." However, the prayer for relief requests enhanced damages pursuant to 35 U.S.C. § 284, a remedy typically predicated on a finding of willful or egregious infringement (Compl. p. 11, ¶7). The complaint does not plead facts supporting pre-suit knowledge of the patents by the Defendant.
VII. Analyst’s Conclusion: Key Questions for the Case
- A threshold procedural question is the viability of the '743 patent claim: Given that all claims of the ’743 patent were cancelled in an IPR proceeding that concluded after the complaint was filed, the court must determine how to proceed with the third count of the complaint, which is now based on a patent with no enforceable claims.
- A key evidentiary question for the ’480 patent will be one of operational architecture: Does discovery show that the accused IDT SRAM achieves dual-port functionality using the claimed method of sequentially accessing a single-port core within one external clock cycle, or does it utilize a fundamentally different, non-infringing internal design?
- For the ’972 patent, the case may turn on a question of structural conformity: Will a physical analysis of the accused DDR4 Register package confirm that its encapsulant is a "singular polymeric body" with "sides coextensive with said carrier sides," or will it reveal a construction or geometry that falls outside these precise structural limitations?