DCT
8:17-cv-01833
North Star Innovations Inc v. Kingston Technology Co Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: North Star Innovations Inc. (Delaware)
- Defendant: Kingston Technology Company, Inc. (Delaware)
- Plaintiff’s Counsel: Law Office of Ryan E. Hatch, PC; Whitaker Chalk Swindle & Schwartz PLLC
- Case Identification: 8:17-cv-01833, C.D. Cal., 07/09/2018
- Venue Allegations: Plaintiff alleges venue is proper in the Central District of California because Defendant conducts regular business and has committed the alleged acts of infringement in the district.
- Core Dispute: Plaintiff alleges that Defendant’s DDR3 and DDR3L SDRAM memory products infringe four patents related to semiconductor memory circuit architecture, voltage conversion, and power management.
- Technical Context: The patents-in-suit address fundamental challenges in modern semiconductor memory design, including signal amplification, on-chip voltage regulation, and the reduction of power leakage.
- Key Procedural History: The complaint is a First Amended Complaint, indicating prior motion practice. Subsequent to the filing of this complaint, Inter Partes Review (IPR) proceedings at the USPTO resulted in the cancellation of all asserted claims for three of the four patents-in-suit ('274, '875, and '555 Patents). The asserted claims of the '145 Patent (Claims 1 and 6) survived IPR.
Case Timeline
| Date | Event |
|---|---|
| 1998-02-02 | '274 Patent Priority Date |
| 1998-08-13 | '875 Patent Priority Date |
| 1998-12-21 | '145 Patent Priority Date |
| 1999-08-24 | '274 Patent Issued |
| 2000-08-08 | '145 Patent Issued |
| 2000-10-03 | '875 Patent Issued |
| 2003-09-30 | '555 Patent Priority Date |
| 2005-07-12 | '555 Patent Issued |
| 2018-04-27 | IPR filed against '274 Patent (IPR2018-00989) |
| 2018-05-01 | IPRs filed against '875 Patent (IPR2018-00998, -00999) |
| 2018-07-09 | First Amended Complaint Filed |
| 2018-09-24 | IPR filed against '145 Patent (IPR2018-01784) |
| 2018-09-25 | IPR filed against '555 Patent (IPR2018-01794) |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 5,943,274 - “Method and Apparatus For Amplifying a Signal to Produce A Latched Digital Signal,” issued August 24, 1999
The Invention Explained
- Problem Addressed: The patent describes a problem in prior art memory output stages that used two separate clock signals to first clock a differential amplifier and then clock a data latch. The patent asserts that maintaining a precise timing relationship between these two clocks is difficult due to variations in manufacturing, temperature, and power supply, which can lead to unreliable operation ('274 Patent, col. 2:21-41).
- The Patented Solution: The invention proposes an output stage circuit that requires only one clock signal to function, thereby avoiding the timing skew problem between two clocks ('274 Patent, col. 2:42-45). The circuit uses a differential amplifier and a level converter to process the incoming data signal, and a "clock-free latch" to hold the resulting digital signal without needing a separate, dedicated clock signal for the latching function ('274 Patent, Abstract; FIG. 2).
- Technical Importance: This design sought to improve the speed and reliability of memory output stages by eliminating a potential source of timing errors common in high-speed circuit designs ('274 Patent, col. 2:38-41).
Key Claims at a Glance
- The complaint asserts independent Claim 1, which was subsequently cancelled in an IPR proceeding ('274 IPR Certificate).
- The essential elements of asserted Claim 1 are:
- An apparatus for use as an output stage of a memory device, comprising:
- a timing circuit;
- a differential amplifier responsive to the timing circuit;
- an impedance control circuit;
- a level converter responsive to the differential amplifier and the impedance control circuit; and
- a clock-free latch responsive to the level converter.
- The complaint reserves the right to assert additional claims (Compl. ¶ 26).
U.S. Patent No. 6,127,875 - “Complimentary Double Pumping Voltage Boost Converter,” issued October 3, 2000
The Invention Explained
- Problem Addressed: Many integrated circuits require an on-chip voltage supply that is higher than the main supply voltage. The patent notes that prior art voltage boosting circuits often produced an output with significant ripple or distortion, as the voltage would decay while delivering current to the load ('875 Patent, col. 1:49-54).
- The Patented Solution: The invention describes a "complimentary double pumping" voltage booster. This architecture uses two symmetric boost circuits that operate 180 degrees out of phase ('875 Patent, col. 2:31-38). While one circuit delivers a boosted voltage to the output, the complementary circuit is simultaneously being charged. This ensures that a boosted voltage is supplied to the load during each half of the clock cycle, which smooths the output voltage and reduces ripple ('875 Patent, Abstract; FIG. 3).
- Technical Importance: This approach allows for a more stable, efficient, and compact on-chip high-voltage supply, which is critical for functions like driving memory word lines, while requiring less total capacitance and thus less die area ('875 Patent, col. 3:1-14).
Key Claims at a Glance
- The complaint asserts independent Claim 1, which was subsequently cancelled in an IPR proceeding ('875 IPR Certificate).
- The essential elements of asserted Claim 1 are:
- A boost circuit having an input terminal and an output terminal, comprising:
- a first switch coupled between the input terminal and the output terminal and operated by a first phase signal;
- a second switch coupled between the input terminal and the output terminal and operated by a second phase signal that is opposite to the first phase signal;
- a first capacitor having a first terminal coupled to the output terminal and a second terminal coupled for receiving a boost signal; and
- a second capacitor having a first terminal coupled to the output terminal and a second terminal coupled for receiving the boost signal.
- The complaint reserves the right to assert additional claims (Compl. ¶ 36).
U.S. Patent No. 6,917,555 - “Integrated Circuit Power Management for Reducing Leakage Current in Circuit Arrays and Method Therefor,” issued July 12, 2005
- Technology Synopsis: The patent addresses the problem of static power leakage in memory arrays when an integrated circuit is idle. The described solution creates separate power planes, allowing the main data arrays of a memory to be completely powered down to save power, while keeping essential control circuitry and the processor core active ('555 Patent, Abstract; col. 2:9-24).
- Asserted Claims: The complaint asserts independent Claim 15, which was subsequently cancelled in an IPR proceeding ('555 IPR Certificate) (Compl. ¶ 42).
- Accused Features: The complaint alleges that the accused DDR3 memory products incorporate power management capabilities, such as power-down modes, that utilize multiple, independent power planes to reduce or eliminate leakage current (Compl. ¶¶ 43-44).
U.S. Patent No. 6,101,145 - “Sensing Circuit and Method,” issued August 8, 2000
- Technology Synopsis: The patent seeks to reduce unwanted "glitches" (invalid data transitions) on a memory's output data bus. The invention proposes a "self-controlled" sense amplifier that is triggered by the voltage swing on the memory bit lines themselves, ensuring it does not activate until valid data is ready ('145 Patent, Abstract). Additionally, for multi-block memories, it describes a feedback circuit that preloads the latches of inactive memory blocks with the currently valid data on the output bus, preventing glitches when switching between blocks ('145 Patent, col. 2:59-65).
- Asserted Claims: The complaint asserts independent Claims 1 and 6, which survived IPR review ('145 IPR Certificate) (Compl. ¶ 53).
- Accused Features: The complaint alleges the accused products use a self-controlled sense amplifier to eliminate the need for external timing signals and a feedback circuit to prevent invalid data transitions upon activation (Compl. ¶ 54).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Kingston's DDR3 and DDR3L SDRAM memory products and families, including but not limited to specific parts such as the 4Gb DDR3L SDRAM (Part No. D5128EETBPGGBU) and the 8GB DDR3L SODIMM (Part#: KVR16LS11/8) (Compl. ¶ 20).
Functionality and Market Context
- The complaint characterizes the accused products as volatile memory devices, such as DRAM and SDRAM, that incorporate specific circuit designs for signal amplification, voltage boosting, and power management (Compl. ¶¶ 10, 22, 33, 43, 54). The complaint alleges that Defendant Kingston is the "world's largest independent manufacturer of memory products" and "commands nearly 65% of the worldwide market" for third-party DRAM modules, suggesting significant commercial importance (Compl. ¶ 3).
IV. Analysis of Infringement Allegations
'274 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an apparatus for use as an output stage of a memory device... | The Accused Product is a memory device that includes an output stage. A reverse-engineered schematic shows an apparatus for use as an output stage of a memory device (Compl. ¶ 23). | ¶22, ¶23 | col. 4:50-53 |
| a timing circuit; | The Accused Product allegedly includes a timing circuit. The complaint does not map this element to a specific structure in its schematics but asserts its presence as part of an improved design. | ¶21 | col. 6:65-col. 7:4 |
| a differential amplifier responsive to the timing circuit; | The Accused Product allegedly includes a differential amplifier. The complaint provides a reverse-engineered schematic labeled "Read Sense Amplifier" (Compl. ¶ 23). | ¶21, ¶23 | col. 6:65-67 |
| an impedance control circuit; | The Accused Product allegedly includes an impedance control circuit. The complaint does not map this element to a specific structure but alleges its presence. | ¶21 | col. 6:67-68 |
| a level converter responsive to the differential amplifier and the impedance control circuit; and | The Accused Product allegedly includes a level converter. The complaint does not map this element to a specific structure but alleges its presence. | ¶21 | col. 7:1-3 |
| a clock-free latch responsive to the level converter. | The Accused Product allegedly includes a clock-free latch. The complaint provides a schematic labeled "FlipFlop without clock" (Compl. ¶ 23) and another showing the logic gates of the latch (Compl. ¶ 24). | ¶21, ¶24 | col. 7:5-7 |
- Identified Points of Contention:
- Overarching Legal Question: The primary issue is that asserted Claim 1 of the '274 Patent has been cancelled by the USPTO in an IPR proceeding, which may render this count moot.
- Evidentiary Question: The complaint's infringement allegations are largely conclusory, block-quoting claim language and asserting that the accused product "includes" the recited elements without mapping them to specific components in the provided schematics (Compl. ¶ 21). The complaint relies on an external "preliminary claim chart" (Ex. E) that is not attached to the pleading, raising a question of whether the allegations meet the plausibility standard required by Iqbal/Twombly.
- Technical Question: It raises the question of whether the circuit blocks identified in the reverse-engineered schematics, such as the "Read Sense Amplifier," perform the specific functions and have the specific interconnections required by the claim language.
'875 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A boost circuit having an input terminal and an output terminal... | The Accused Product allegedly includes an efficient and compact voltage boosting circuit. The complaint includes a reverse-engineered schematic that allegedly shows a boost circuit (Compl. ¶ 34). | ¶33, ¶34 | col. 1:15-20 |
| a first switch coupled between the input terminal and the output terminal and operated by a first phase signal; | The Accused Product allegedly includes this element. The complaint does not map this recited switch to a specific component in the provided schematic. | ¶32 | col. 6:10-12 |
| a second switch coupled between the input terminal and the output terminal and operated by a second phase signal that is opposite to the first phase signal; | The Accused Product allegedly includes this element. The complaint does not map this recited switch to a specific component in the provided schematic. | ¶32 | col. 6:12-15 |
| a first capacitor having a first terminal coupled to the output terminal and a second terminal coupled for receiving a boost signal; and | The Accused Product allegedly includes this element. The provided schematic shows numerous capacitors, but the complaint does not identify which corresponds to this claim limitation (Compl. ¶ 34). | ¶32, ¶34 | col. 6:15-18 |
| a second capacitor having a first terminal coupled to the output terminal and a second terminal coupled for receiving the boost signal. | The Accused Product allegedly includes this element. The provided schematic shows numerous capacitors, but the complaint does not identify which corresponds to this claim limitation (Compl. ¶ 34). | ¶32, ¶34 | col. 6:1-3 |
- Identified Points of Contention:
- Overarching Legal Question: As with the '274 Patent, asserted Claim 1 of the '875 Patent has been cancelled by the USPTO in an IPR proceeding, which may render this count moot.
- Scope Question: The claim recites a "first switch" and a "second switch" both being "coupled between the input terminal and the output terminal." This raises a question of claim scope, as this specific topology may not align with the actual operation of either the patented embodiment or the accused product, where switches typically route signals to or from intermediate nodes rather than directly bridging the main input and output.
- Evidentiary Question: The complaint's allegations are conclusory and rely on an unattached claim chart exhibit (Ex. F) (Compl. ¶ 35). It presents a complex schematic but fails to explain how the components within it meet the specific limitations of Claim 1, raising questions about pleading sufficiency.
V. Key Claim Terms for Construction
'274 Patent
- The Term: "clock-free latch"
- Context and Importance: This term is central to the patent's asserted novelty over prior art that required multiple, precisely timed clock signals. The definition of "clock-free" will determine whether the structure is limited to the specific embodiment or covers any latch that does not receive a direct clock input.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not appear to provide an explicit definition of the term. A party could argue it should be given its plain and ordinary meaning: a latching circuit that does not require a clock signal for its operation.
- Evidence for a Narrower Interpretation: The patent describes the latch's function in a specific context: "Clock-free latch 106 will then store that new value even when level converter 102 is subsequently disabled" ('274 Patent, col. 6:41-43). The specification's only embodiment shows it as cross-coupled inverters (144, 145) that are responsive to the output of the level converter, suggesting its meaning is tied to this specific circuit arrangement and function ('274 Patent, col. 5:5-7).
'875 Patent
- The Term: "a ... switch coupled between the input terminal and the output terminal"
- Context and Importance: Claim 1 recites two separate switches that are both described as being coupled "between" the input and output terminals. This is a critical structural limitation. Its construction will determine whether the claim reads on a conventional boost converter topology, including the one shown in the patent's own figures.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader (or Different) Interpretation: A party might argue that in the context of the patent, "between" does not mean a direct, uninterrupted connection but rather describes the switch's role in the overall current path from the input to the output.
- Evidence for a Narrower (Literal) Interpretation: The plain language suggests a direct coupling. The patent's own embodiment in FIG. 3 shows switches (e.g., 42A, 52A) that are in series along the path from input to output but are separated by an intermediate node and a capacitor, not directly coupled between the ultimate input and output terminals. This apparent inconsistency between the claim language and the specification's embodiment suggests a significant point of dispute over the claim's scope.
VI. Other Allegations
Indirect Infringement
- The complaint does not plead specific facts to support a claim for indirect infringement. It makes no allegations regarding Defendant's specific intent or knowledge, nor does it identify any specific instructions (e.g., in user manuals) that would encourage or instruct end-users to infringe.
Willful Infringement
- The complaint does not allege any facts that would support a claim of willful infringement, such as alleged pre-suit knowledge of the patents or egregious conduct. The prayer for relief requests enhanced damages and a finding of an exceptional case, but the body of the complaint lacks the factual predicate for such claims (Compl. p. 17, ¶¶ 6-7).
VII. Analyst’s Conclusion: Key Questions for the Case
- The Impact of IPR: The central and dispositive issue for three of the four patents ('274, '875, '555) is that the only asserted claims have been cancelled by the USPTO. A key question is whether the litigation on these patents can proceed, as the legal basis for the infringement counts appears to have been eliminated.
- The Viability of the Sole Remaining Patent: For the '145 Patent, whose asserted claims survived IPR, the case will likely turn on a question of technical and evidentiary proof. Can the plaintiff demonstrate that Kingston’s DDR3L memory products, which conform to broad industry standards, implement the specific "self-controlled sense amplifier" and "feedback circuit for preloading inactive blocks" as required by the claims, or is there a fundamental mismatch in technical operation?
- Pleading Sufficiency: A threshold question for the entire case is one of procedural compliance: does the complaint, which makes largely conclusory allegations and relies heavily on unincorporated and unattached exhibits, state a plausible claim for relief under the Iqbal/Twombly standard, particularly for the highly technical elements of the asserted claims?