DCT
8:21-cv-00284
Xiaohua Huang v. Enterasource LLC
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Xiaohua Huang (California)
- Defendant: Enterasource, LLC (California)
- Plaintiff’s Counsel: Pro Se
- Case Identification: 8:21-cv-00284, C.D. Cal., 02/12/2021
- Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains an operational office and conducts regular business within the Central District of California.
- Core Dispute: Plaintiff alleges that Defendant’s networking switches and routers infringe two patents related to circuit designs and methods for Content Addressable Memory (CAM).
- Technical Context: Content Addressable Memory is a specialized type of high-speed memory used in networking equipment to accelerate search-intensive functions like packet forwarding, routing lookups, and access control list enforcement.
- Key Procedural History: The complaint alleges that Plaintiff sent a letter to Defendant in December 2020 informing it of the patents and alleged infringement, and that Plaintiff had not received a response prior to filing suit.
Case Timeline
| Date | Event |
|---|---|
| 2001-10-04 | U.S. Patent No. 6,744,653 Priority Date |
| 2004-03-04 | U.S. Patent No. RE45,259 E Priority Date |
| 2004-06-01 | U.S. Patent No. 6,744,653 Issues |
| 2014-11-25 | U.S. Patent No. RE45,259 E Issues |
| 2020-12-XX | Plaintiff allegedly mails letter to Defendant |
| 2021-02-12 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,744,653 - CAM cells and differential sense circuits for content addressable memory (CAM)
- Patent Identification: U.S. Patent No. 6,744,653, titled "CAM cells and differential sense circuits for content addressable memory (CAM)," issued on June 1, 2004 (the "’653 Patent").
The Invention Explained
- Problem Addressed: The patent’s background section describes performance limitations in conventional CAMs related to speed and power consumption. Specifically, when a long "match line" in a CAM array must be fully discharged to signal a mismatch, the process can be slow and consume excessive power (’653 Patent, col. 1:55-2:10).
- The Patented Solution: The invention proposes a differential sensing technique to more quickly and efficiently determine a match or mismatch. The solution involves adding a "dummy CAM cell" and an associated "dummy line" to each row of the CAM array to generate a reference voltage (’653 Patent, Abstract; col. 2:23-39). A sense circuit then rapidly detects the small voltage difference between the actual match line and the reference dummy line, avoiding the need for a full voltage swing on the match line and thereby improving speed and reducing power usage (’653 Patent, col. 2:35-39).
- Technical Importance: This differential sensing approach sought to ameliorate the speed and power bottlenecks in CAMs, which are critical for performance in high-speed networking devices (’653 Patent, col. 2:11-14).
Key Claims at a Glance
- The complaint asserts at least independent claim 17 of the ’653 Patent (Compl. ¶14).
- The essential elements of independent claim 17 include:
- A method for sensing a logic state of a match line in a CAM
- sensing a signal on a first common line related to the match line signal
- providing a reference signal on a second common line based on dummy transistors
- determining a difference between the sensed signal and the reference signal
- amplifying the difference with a positive feedback amplifier
- providing an output value indicating the logic state based on the amplified difference
U.S. Reissue Patent No. RE45,259 E - Hit ahead hierarchical scalable priority encoding logic and circuits
- Patent Identification: U.S. Reissue Patent No. RE45,259 E, titled "Hit ahead hierarchical scalable priority encoding logic and circuits," issued on November 25, 2014 (the "’RE259 Patent").
The Invention Explained
- Problem Addressed: The patent’s background section explains that when a CAM search yields multiple simultaneous matches (a "multi-hit"), a priority encoding circuit is required to select the single highest-priority result. For large CAMs, the logic calculations for this encoding process can introduce significant delay, creating a performance bottleneck (’RE259 Patent, col. 1:21-33, 58-63).
- The Patented Solution: The invention discloses a "Hit Ahead Priority Encoding" (HAPE) architecture. This hierarchical method speeds up priority resolution by generating a simple "hit signal" at a first level of logic to immediately inform the next level, rather than waiting for the full priority encoding computation to complete. This allows for parallel processing between levels, reducing the overall time needed to identify the highest-priority match (’RE259 Patent, Abstract; col. 2:7-14).
- Technical Importance: This "hit ahead" technique was designed to accelerate priority encoding in large, high-density CAMs, a key requirement for maintaining performance in network routers and switches operating at high data rates (’RE259 Patent, col. 2:3-6).
Key Claims at a Glance
- The complaint asserts at least independent claim 29 of the ’RE259 Patent (Compl. ¶20).
- The essential elements of independent claim 29 include:
- A CAM system comprising a circuit segment
- The circuit segment is configured to generate an output based on whether at least one input corresponds to a first logic level
- The circuit segment is also configured to set a node to a second logic level (e.g., pre-charge) in response to an input signal, and subsequently change the node to a third logic level (e.g., discharge) in response to circuit inputs
- The circuit segment output corresponds to the third logic level
III. The Accused Instrumentality
Product Identification
- The complaint identifies a range of networking products, including but not limited to switches and routers such as the EX2200, EX4300, QFX5100, and MX480 (Compl. ¶11).
Functionality and Market Context
- The complaint alleges that Defendant is a reseller of networking switches and routers (Compl. ¶3, ¶10). It further alleges that these products contain integrated circuits (ICs) with Ternary Content Addressable Memory (TCAM) that implement infringing functionality (Compl. ¶6, ¶11).
- The complaint provides a schematic titled "Figure 1. CAM differential sensing circuit," which it alleges represents a circuit within the accused products for performing differential sensing (Compl. p. 4). A second schematic, "Figure 2. the IC circuit in CAM and other function," is also provided (Compl. p. 4).
- The complaint alleges the accused TCAM circuits are used to perform fundamental networking functions such as Access Control Lists (ACL) and Quality of Service (QoS) (Compl. ¶16, ¶22).
IV. Analysis of Infringement Allegations
’653 Patent Infringement Allegations
| Claim Element (from Independent Claim 17) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| sensing a signal on a first common line, wherein the signal on the first common line is related to a signal on the match line | The accused circuit reads the signal on the "1st common line" which is connected to the match line via N-transistors. | ¶11, p. 5 | col. 13:3-12 |
| providing a reference signal on a second common line based on a plurality of dummy transistors | The accused circuit reads the signal on the "2nd common line" which is connected to a dummy line via N-transistors. | ¶11, p. 5 | col. 13:13-18 |
| determining a difference between the sensed signal on the first common line and the reference signal on the second common line | The "1st common line" and "2nd common line" serve as inputs to a differential amplifier. | ¶11, p. 6 | col. 13:41-48 |
| amplifying the determined difference with a positive feedback amplifier | The differential amplifier amplifies the difference between the two common line inputs. | ¶11, p. 6 | col. 7:51-54 |
| providing an output value indicative of the logic state of the match line based on the amplified difference | The differential amplifier provides an output value based on the amplified difference of its inputs. | ¶11, p. 6 | col. 8:12-14 |
- Identified Points of Contention:
- Evidentiary Question: The complaint's infringement theory relies on the schematic in its "Figure 1," but it does not specify the source of this information (e.g., reverse engineering, public datasheets) (Compl. ¶11). A central question will be whether the plaintiff can produce evidence that this schematic accurately represents the circuitry present in the accused products.
- Scope Question: The analysis will question whether the "Differential Amplifier" shown in the complaint's Figure 1 meets the claim limitation of a "positive feedback amplifier." While many differential amplifiers incorporate positive feedback, the term's construction may become a point of dispute.
’RE259 Patent Infringement Allegations
| Claim Element (from Independent Claim 29) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level | The output voltage of the accused circuit in Figure 2 and the voltage on the "1st common line" in Figure 1 depend on the logic level of the input signals to the N-transistors. | ¶11, p. 7 | col. 9:4-10 |
| the circuit segment configured to set a node to a second logic level in response to an input signal | The output nodes in Figure 2 and the common line in Figure 1 are first set to a high or low logic level before the input signals arrive. | ¶11, p. 7 | col. 5:58-65 |
| and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs | The logic level of the output nodes and common line will subsequently change depending on the logic level of the input signals to the N-transistors. | ¶11, p. 7 | col. 5:58-65 |
| the circuit segment output corresponding to said third logic level | The change in the output follows the arrival of the input signal to the N-transistors. | ¶11, p. 7 | col. 9:45-50 |
- Identified Points of Contention:
- Technical Question: The complaint's allegations map the claim elements to the high-level behavior of the circuits in Figures 1 and 2 (Compl. p. 7). A potential dispute is whether this high-level functional description satisfies the specific sequence of operations and configurations recited in claim 29.
- Scope Question: Claim 29 uses broad terms like "circuit segment" and "logic level." The infringement analysis may turn on whether these terms are given a general meaning or are construed more narrowly in light of the patent's overall disclosure of a hierarchical priority encoding system.
V. Key Claim Terms for Construction
’653 Patent: "positive feedback amplifier" (Claim 17)
- The Term: "positive feedback amplifier"
- Context and Importance: This term defines the core amplifying mechanism of the claimed sensing method. Its construction will determine which circuit architectures can be found to infringe. The complaint alleges a "Differential Amplifier" meets this limitation (Compl. p. 4, Figure 1).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim uses the general term "positive feedback amplifier," which a plaintiff may argue should be given its plain and ordinary meaning, covering any amplifier where a portion of the output signal is fed back to the input to increase gain.
- Evidence for a Narrower Interpretation: The specification’s primary embodiment of this element is a pair of cross-coupled inverters (e.g., ’653 Patent, Fig. 3C, 412a/412b). A defendant may argue that the term should be limited to this disclosed structure or its equivalents.
’RE259 Patent: "circuit segment" (Claim 29)
- The Term: "circuit segment"
- Context and Importance: This term is the foundational element of claim 29. The breadth of its definition is central to the infringement analysis, as the complaint maps this single term to two different alleged circuits (the circuit in Figure 2 and the common line circuit in Figure 1) (Compl. p. 7).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not explicitly define "circuit segment," which may support an argument that the term should be afforded its broad, ordinary meaning in the field of circuit design.
- Evidence for a Narrower Interpretation: A defendant may argue that the term must be read in the context of the patent's title and abstract, which focus on "hierarchical scalable priority encoding." This could support a narrower construction where a "circuit segment" must be a component that performs a function related to priority encoding, rather than any generic circuit.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement and contributory infringement for both patents. The allegations are based on Defendant's selling of products for their intended networking functions (e.g., ACL and QoS) and the assertion that the accused TCAM circuits are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶15-16, ¶21-22).
- Willful Infringement: The complaint does not contain an explicit count for willful infringement. However, it alleges that Plaintiff provided pre-suit notice to Defendant of the patents-in-suit via a letter in December 2020 (Compl. ¶1). This allegation may form the basis for a future claim of willfulness, particularly for any infringement occurring after Defendant received the alleged notice.
VII. Analyst’s Conclusion: Key Questions for the Case
- A primary issue will be one of evidentiary proof: can the plaintiff substantiate its claim that the accused networking products, sold by a reseller, contain the specific circuit architectures depicted in the complaint’s schematics? The complaint's failure to cite the source of these schematics suggests this will be a central point of discovery and contention.
- A key technical question will be one of functional mapping: assuming the accused circuits exist as alleged, does their high-level operation, as described in the complaint’s conclusory claim charts, satisfy every limitation of the asserted claims? This is particularly relevant for the broad, functional language of claim 29 of the ’RE259 Patent.
- A core legal question will be one of claim construction: can the broad term "circuit segment" in the ’RE259 Patent be interpreted to read on the generic circuit elements alleged by the plaintiff, or will it be narrowed by the court to structures that perform the patent’s disclosed "Hit Ahead Priority Encoding" function?