DCT
8:22-cv-01823
Bell Semiconductor LLC v. Western Digital Tech Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Western Digital Technologies, Inc. (California)
- Plaintiff’s Counsel: McKool Smith, P.C.
- Case Identification: 8:22-cv-01823, C.D. Cal., 10/05/2022
- Venue Allegations: Plaintiff alleges venue is proper in the Central District of California because Defendant maintains a "regular and established place of business" in Irvine, CA, employs a substantial number of engineers there, and commits the alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal processes for designing semiconductor chips infringe a patent related to methods for efficiently implementing engineering change orders.
- Technical Context: The technology concerns electronic design automation (EDA) for integrated circuits, a field where minimizing the time and computational resources required to modify and verify complex chip designs is critical for time-to-market.
- Key Procedural History: The complaint notes that Plaintiff Bell Semiconductor, LLC is a successor to the patent portfolios of Bell Labs, Lucent Technologies, Agere Systems, and LSI Corporation. No other specific procedural events, such as prior litigation or administrative proceedings involving the patent-in-suit, are mentioned.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | ’626 Patent Priority Date |
| 2007-06-12 | ’626 Patent Issue Date |
| 2022-10-05 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows”
- Patent Identification: U.S. Patent No. 7,231,626, “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows,” issued June 12, 2007.
The Invention Explained
- Problem Addressed: The patent’s background section describes that prior art methods for implementing an engineering change order (ECO) in a complex integrated circuit (IC) design were highly inefficient. Because design verification tools like routing and rule checkers typically "scale with the size of the entire integrated circuit design," making even a small change required re-running these time-consuming processes for the whole chip, which could take "about one week regardless of the size of the engineering change order" (’626 Patent, col. 2:15-22, 2:39-41).
- The Patented Solution: The invention proposes a method to localize the design and verification work. It involves creating a "window" that geometrically encloses only the portion of the IC design affected by the ECO (’626 Patent, Abstract). Instead of re-processing the entire design, the patented method performs "incremental routing" and other checks "only for each net in the integrated circuit design that is enclosed by the window" (’626 Patent, col. 6:50-54). The results from this localized process are then merged back into a copy of the original design to create a revised version, significantly reducing the required computational effort and time (’626 Patent, col. 4:18-24; Fig. 2).
- Technical Importance: This approach allows for "significant savings in the resources required to perform routing, design rule check verification, net delay calculation, and parasitic extraction" by avoiding the need to re-validate the entire, unchanged portion of the chip design (’626 Patent, col. 3:18-23).
Key Claims at a Glance
- The complaint asserts infringement of one or more claims, with a focus on independent claim 1 (Compl. ¶¶30, 37).
- The essential elements of independent claim 1 are:
- Receiving as input an integrated circuit design and an engineering change order.
- Creating at least one "window" that encloses the change, where the window's area is less than the entire area of the circuit design.
- Performing "incremental routing" of the design "only for each net...that is enclosed by the window."
- "Replacing an area in a copy" of the design with the results of the incremental routing to generate a revised design.
- Generating the revised integrated circuit design as output.
- The complaint does not explicitly reserve the right to assert dependent claims, but the general allegation of infringing "one or more claims" suggests this possibility (Compl. ¶37).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the accused instrumentality not as a final product, but as the "Accused Processes" used by Western Digital to design its semiconductor devices (Compl. ¶38). The complaint names the "WD Black SN 850 NVMe SSD" as one example of a product produced using these allegedly infringing processes (Compl. ¶10).
Functionality and Market Context
- The complaint alleges that Western Digital's "Accused Processes" employ a variety of industry-standard EDA design tools from vendors such as Cadence, Synopsys, and/or Siemens (Compl. ¶¶38, 40). These processes are alleged to perform incremental routing, calculate parasitic extraction, and run design rule checks "only for each net in the IC design enclosed by the window defining the ECO" (Compl. ¶¶38-40). This description frames the accused processes as a method for efficiently implementing design changes by localizing the necessary computational work, mirroring the functionality described in the ’626 patent.
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| creating at least one window in the integrated circuit design that encloses a change...wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design | Western Digital's Accused Processes allegedly define a "window" enclosing an ECO to perform localized design rule checks and parasitic extractions. | ¶¶39, 40 | col. 6:42-49 |
| performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window | The Accused Processes allegedly use design tools to perform incremental routing only for the nets affected by the ECO and located within the defined window. | ¶38 | col. 6:50-54 |
| replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design | The Accused Processes are alleged to merge the changed area into the overall circuit layout to generate a revised design. | ¶38 | col. 6:55-60 |
| generating as output the revised integrated circuit design | The Accused Processes are alleged to generate a revised integrated circuit design for the Western Digital Accused Product. | ¶38 | col. 6:61-62 |
- Identified Points of Contention:
- Technical Questions: A primary question will be whether the operation of the commercial EDA tools (e.g., Cadence, Synopsys) used by Western Digital, as configured in the "Accused Processes," performs the specific steps recited in the claim. The complaint alleges these tools are used to perform the claimed method (Compl. ¶¶38-40), but the extent to which their default or customized functionality matches the patent’s description of "incremental routing" and "replacing an area in a copy" will be a central factual dispute.
- Scope Questions: The complaint's infringement theory relies on mapping the claims onto processes that use third-party software. This raises the question of whether the term "window", as claimed, reads on the specific data structures or selection methods used by these commercial tools to define a work area.
V. Key Claim Terms for Construction
The Term: "window"
Context and Importance: This term is the lynchpin of the invention, as it defines the limited area where the efficiency-gaining operations occur. Its construction will determine whether the method by which the accused processes isolate design changes falls within the scope of the claims. Practitioners may focus on this term because the patent provides specific details about its nature that could be used to argue for a narrower construction than the plain language might suggest.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Claim 1 defines the "window" broadly as being "bounded by coordinates that define an area that is less than an entire area of the integrated circuit design" (’626 Patent, col. 6:46-49). This language does not appear to limit the shape or method of creation.
- Evidence for a Narrower Interpretation: The specification defines a "window" as a "rectilinear boundary" (’626 Patent, col. 4:59-60) and describes a detailed process for its creation, including calculating bounding boxes and merging them (’626 Patent, Fig. 3, col. 4:54-col. 5:12). A party could argue that the term should be limited to such rectilinear embodiments.
The Term: "incremental routing"
Context and Importance: This term describes the core work-saving action of the claimed method. The dispute will likely center on what specific operations must be included (or excluded) for a routing process to be considered "incremental" as claimed.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim requires performing the routing "only for each net in the integrated circuit design that is enclosed by the window" (’626 Patent, col. 6:52-54), contrasting it with routing the entire design. This could be interpreted as any routing process that is spatially limited to the window.
- Evidence for a Narrower Interpretation: The specification provides additional details, stating that "only the nets that are modified by the engineering change order are routed" and that if a net is not fully contained in the window, it is "'frozen', which means that the net may not be changed by the router" (’626 Patent, col. 4:6-8, 4:13-15). This suggests "incremental routing" might require specific logic for handling partially-enclosed nets, potentially narrowing the claim's scope.
VI. Other Allegations
- Indirect Infringement: The complaint includes a general allegation of direct and indirect infringement "pursuant to 35 U.S.C. § 271, et. seq." (Compl. ¶43). However, it does not plead specific facts to support a claim for either induced or contributory infringement, such as allegations of instructing others or providing a non-staple component for infringement. The factual allegations focus on direct infringement by Western Digital's use of the "Accused Processes" (Compl. ¶37).
- Willful Infringement: The complaint does not use the word "willful" but does allege that the infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶44). The complaint does not allege any facts to support pre-suit knowledge of the patent or its infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of evidentiary proof: can Plaintiff demonstrate that the complex, multi-step operations of the commercial EDA software used by Defendant perform a sequence of steps that maps directly onto the limitations of Claim 1? The case may depend on technical evidence from discovery detailing how these third-party tools are specifically configured and used within Defendant's "Accused Processes."
- The case will also turn on a question of claim construction: can the term "window", as used in the patent, be construed broadly enough to read on the various methods that commercial software might use to select a region of interest, or will it be limited to the "rectilinear boundary" described in a specific embodiment of the patent? The outcome of this construction could be dispositive for infringement.