DCT
8:22-cv-02124
Bell Semiconductor LLC v. Kioxia Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Kioxia America, Inc. (California) and Kioxia Corporation (Japan)
- Plaintiff’s Counsel: Devlin Law Firm LLC
- Case Identification: 8:22-cv-02124, C.D. Cal., 11/22/2022
- Venue Allegations: Plaintiff alleges venue is proper because Kioxia has a regular and established place of business in the district, including a sales office in Irvine, CA with at least 65 employees, and has committed acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor chips and packages infringe patents related to integrated circuit packaging structures and manufacturing methods designed to reduce signal degradation.
- Technical Context: The technology addresses parasitic capacitance in high-speed, multi-layer semiconductor packages, a phenomenon that can distort signals and limit the maximum operating frequency of a device.
- Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement of the ’269 patent on March 26, 2020, and of the ’340 patent on June 3, 2022, forming the basis for allegations of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2006-03-22 | Priority Date for ’340 and ’269 Patents |
| 2011-11-01 | U.S. Patent No. 8,049,340 Issues |
| 2012-10-16 | U.S. Patent No. 8,288,269 Issues |
| 2020-03-26 | Alleged Actual Notice of ’269 Patent to Kioxia |
| 2022-06-03 | Alleged Actual Notice of ’340 Patent to Kioxia |
| 2022-11-22 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,049,340 - Device for Avoiding Parasitic Capacitance in an Integrated Circuit Package
- Patent Identification: U.S. Patent No. 8,049,340, issued November 1, 2011. (Compl. ¶15).
The Invention Explained
- Problem Addressed: In high-speed integrated circuits, such as serializer/deserializer (SERDES) devices, the close proximity of metal layers within the chip package creates "parasitic capacitance." This unwanted capacitance, particularly between signal-carrying contact pads and adjacent ground or routing layers, can distort the signal waveform and reduce the circuit's maximum operating frequency. (Compl. ¶17, ¶19; ’340 Patent, col. 2:52-60).
- The Patented Solution: The invention proposes a specific package substrate structure to mitigate this problem. It introduces "cutouts" (i.e., voids) in the metal of a second conductive layer that is adjacent to a first layer containing the contact pads. These cutouts are positioned to "completely overlap" the contact pads below, thereby removing the conductive material directly opposite the pads and significantly reducing the parasitic capacitance between the layers. (Compl. ¶20; ’340 Patent, col. 4:9-14, 31-41).
- Technical Importance: By reducing parasitic capacitance, the invention enables the use of higher frequency signals, which is critical for increasing data transfer rates in advanced electronics. (Compl. ¶19; ’340 Patent, col. 3:21-27).
Key Claims at a Glance
- The complaint discusses independent claim 1 and dependent claim 2. (Compl. ¶21, ¶22).
- The essential elements of independent claim 1 are:
- An integrated circuit package substrate comprising a first and a second electrically conductive layer separated by an insulating layer with no intermediate conductive layer.
- A plurality of rows of contact pads in the first layer for connecting to a printed circuit board.
- A plurality of cutouts in the second layer to reduce parasitic capacitance.
- Each cutout encloses an electrically insulating area within the second layer.
- Each such insulating area "completely overlaps" a corresponding contact pad, resulting in "substantially no overlap" between the contact pads and the metal in the second layer.
U.S. Patent No. 8,288,269 - Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package
- Patent Identification: U.S. Patent No. 8,288,269, issued October 16, 2012. (Compl. ¶24).
The Invention Explained
- Problem Addressed: The ’269 patent shares an identical specification with the ’340 patent and addresses the same problem of performance degradation due to parasitic capacitance in multi-layer packages. (Compl. ¶26; ’269 Patent, col. 1:7-12, col. 2:55-63).
- The Patented Solution: Where the ’340 patent claims the physical apparatus, the ’269 patent claims the method of manufacturing it. The claimed method involves the steps of forming the first conductive layer with contact pads, forming an insulating layer, and then forming the second conductive layer with the strategically placed cutouts that completely overlap the contact pads to eliminate substantial overlap with the metal in that layer. (Compl. ¶27; ’269 Patent, Abstract).
- Technical Importance: The method provides a manufacturing process for creating semiconductor packages that can operate at higher frequencies than prior art designs. (Compl. ¶29).
Key Claims at a Glance
- The complaint discusses independent claim 1 and dependent claim 2. (Compl. ¶27, ¶28).
- The essential elements of independent method claim 1 are:
- Forming a first electrically conductive layer with a plurality of rows of contact pads.
- Forming an electrically insulating layer on the first layer.
- Forming a second electrically conductive layer over the insulating layer (with no intermediate conductive layer), where the second layer comprises metal and a plurality of cutouts.
- Each cutout encloses an insulating area that "completely overlaps" a corresponding contact pad, resulting in "substantially no overlap" between the contact pads and the metal in the second layer.
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Kioxia Accused Products" as the Kioxia TC58NC1132GTC and TOSHIBA TC58NC1133GTC, as well as products containing them. (Compl. ¶11, ¶33).
Functionality and Market Context
- The complaint alleges these are "semiconductor chips and packages" that use the patented packaging technology. (Compl. ¶9-10). It alleges that Kioxia develops, manufactures, markets, and sells these products in the United States, including within the Central District of California. (Compl. ¶9, ¶13). The complaint does not provide specific technical details about the accused products' internal structure or manufacturing process beyond the general allegation that they embody the patented inventions. No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint references claim charts attached as Exhibits C and D, but these exhibits were not included with the filed complaint. (Compl. ¶34, ¶44). The analysis below is based on the complaint's narrative allegations.
’340 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| An integrated circuit package substrate comprising: a first and a second electrically conductive layer separated from each other by an electrically insulating layer with no intermediate conductive layer therebetween; | The accused products are alleged to be integrated circuit package substrates containing at least two conductive layers separated by an insulating layer as claimed. | ¶9, ¶33 | col. 10:37-40 |
| a plurality of rows of contact pads formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board; | The accused products are alleged to contain a first layer with rows of contact pads for external connection. | ¶9, ¶33 | col. 10:41-45 |
| a plurality of cutouts formed in the second electrically conductive layer for reducing parasitic capacitance between the second electrically conductive layer and the first electrically conductive layer, | The accused products are alleged to contain a second conductive layer formed with cutouts to reduce parasitic capacitance. | ¶9, ¶33 | col. 10:46-53 |
| wherein each cutout encloses an electrically insulating area within the second electrically conductive layer, and | The cutouts in the accused products are alleged to enclose an insulating area within the second conductive layer. | ¶9, ¶33 | col. 10:53-56 |
| wherein each electrically insulating area completely overlaps a corresponding one of the contact pads formed in the first electrically conductive layer such that there is substantially no overlap of the rows of contact pads with metal in the second electrically conductive layer. | The insulating areas created by the cutouts in the accused products are alleged to completely overlap the contact pads to achieve substantially no overlap with the surrounding metal. | ¶9, ¶33 | col. 10:56-62 |
’269 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| forming a first electrically conductive layer including a plurality of rows of contact pads; | Kioxia is alleged to manufacture the accused products by a process that includes forming a first conductive layer with rows of contact pads. | ¶9, ¶43 | col. 5:41-43 |
| forming an electrically insulating layer on the first electrically conductive layer; and | Kioxia's alleged manufacturing process includes forming an insulating layer over the first conductive layer. | ¶9, ¶43 | col. 5:44-46 |
| forming a second electrically conductive layer over the electrically insulating layer such that there is no intermediate conductive layer..., the second electrically conductive layer comprising metal and a plurality of cutouts... | Kioxia's alleged manufacturing process includes forming a second conductive layer containing metal and a plurality of cutouts over the insulating layer. | ¶9, ¶43 | col. 5:47-59 |
| wherein each cutout encloses an electrically insulating area... and wherein each electrically insulating area completely overlaps a corresponding one of the contact pads such that there is substantially no overlap... | Kioxia is alleged to form the cutouts in its manufacturing process such that they create insulating areas that completely overlap the contact pads, resulting in substantially no metal overlap. | ¶9, ¶43 | col. 5:59-67 |
Identified Points of Contention
- Scope Questions: The infringement analysis for both patents may turn on the construction of "substantially no overlap." The question is whether this requires a near-total absence of physical overlap, or if it can be satisfied by a functional standard where some physical overlap exists but parasitic capacitance is still reduced to a meaningful degree. Similarly, the meaning of "completely overlaps" will be critical—does it require perfect geometric alignment and sizing, or does it mean the cutout is sufficient to functionally surround the pad?
- Technical Questions: The complaint provides high-level allegations without specific evidence from the accused products. A central question will be what factual evidence Plaintiff can produce through discovery and reverse engineering to show that the accused Kioxia packages are actually built with the specific layer-and-cutout structure claimed in the ’340 patent, and are manufactured using the steps claimed in the ’269 patent.
V. Key Claim Terms for Construction
The Term: "substantially no overlap"
- Context and Importance: This term is the functional heart of the claims, defining the required structural relationship that leads to the invention's benefit. Its construction will be dispositive for infringement, as it defines the boundary between a prior art package with significant overlap and a patented package with minimal overlap.
- Intrinsic Evidence for a Broader Interpretation: The specification emphasizes the functional result of reducing parasitic capacitance. (e.g., ’340 Patent, col. 4:55-65). Plaintiff may argue that any structure achieving this functional goal meets the "substantially no overlap" requirement, even with minor physical overlap.
- Intrinsic Evidence for a Narrower Interpretation: The term is paired with "completely overlaps," suggesting a strict geometric requirement. ('340 Patent, Claim 1). Defendant may argue that the figures, which show a clear void with no overlap (e.g., Fig. 5), define the term's scope and require a near-zero physical overlap.
The Term: "completely overlaps"
- Context and Importance: This term describes the geometric alignment of the cutout relative to the contact pad. Practitioners may focus on this term because its definition dictates the precision required in the manufacturing process and the physical structure.
- Intrinsic Evidence for a Broader Interpretation: The purpose is to "surround" the pad to avoid capacitance. (’340 Patent, Abstract). Plaintiff may argue that "completely" means the cutout is sufficient to fully enclose the pad's area, preventing a direct capacitive path, without requiring perfect centering or sizing.
- Intrinsic Evidence for a Narrower Interpretation: The patent discloses an embodiment where the cutouts "have the same dimensions as the contact pads," which could be used to argue for a more constrained, one-to-one geometric correspondence. ('340 Patent, col. 10:63-65).
VI. Other Allegations
- Indirect Infringement: The complaint does not plead separate counts for indirect infringement. The infringement allegations are for direct infringement under 35 U.S.C. § 271(a). (Compl. ¶33, ¶43).
- Willful Infringement: The complaint alleges willful infringement for both patents. The allegations are based on Kioxia's alleged continued infringement after receiving actual notice of the patents and Plaintiff's infringement contentions. (Compl. ¶36, ¶46). The notice for the ’269 patent is alleged to have been provided on March 26, 2020, more than two years prior to the suit, while notice for the ’340 patent was provided on June 3, 2022. (Compl. ¶36, ¶46).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: how will the court construe the terms "substantially no overlap" and "completely overlaps"? The case may turn on whether these terms are interpreted as requiring a strict, near-perfect geometric arrangement as depicted in the patent figures, or whether they can be satisfied by a functional standard based on the reduction of parasitic capacitance.
- A key evidentiary question will be one of technical proof: as the complaint is light on product-specific details, the dispute will hinge on what evidence Plaintiff can marshall from discovery and expert reverse engineering to prove that the internal, multi-layer structure of Kioxia's accused packages literally meets the specific geometric limitations of the asserted claims.
- A significant damages question will be one of willfulness: given the allegation that Kioxia was on notice of the ’269 patent for over two years before the suit was filed, the court will have to determine whether Kioxia’s continued accused conduct, if found to be infringing, was objectively reckless, which could lead to an award of enhanced damages.