DCT

8:22-cv-02133

Bell Semiconductor LLC v. NXP USA Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 8:22-cv-02133, C.D. Cal., 11/23/2022
  • Venue Allegations: Venue is alleged based on Defendants committing acts of infringement within the Central District of California and maintaining a regular and established place of business in the district, with specific office locations cited for each defendant.
  • Core Dispute: Plaintiff alleges that semiconductor chips and packages manufactured by NXP and incorporated into products by other defendants infringe patents related to semiconductor packaging designs.
  • Technical Context: The patents address reliability and performance challenges in high-density integrated circuits, including mitigating thermal stress, reducing electromagnetic interference between inductors, and isolating high- and low-speed circuitry.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant NXP with actual notice of its infringement contentions for all three asserted patents on January 30, 2022, which may form the basis for its willfulness claims. Subsequent to the complaint's filing, patent disclaimers were filed for U.S. Patent Nos. 7,345,245 and 7,535,330 in February 2024, narrowing the scope of claims available for assertion in this litigation.

Case Timeline

Date Event
2003-10-08 ’245 Patent Priority Date
2006-04-06 ’091 Patent Priority Date
2006-09-22 ’330 Patent Priority Date
2008-03-18 ’245 Patent Issue Date
2009-05-19 ’330 Patent Issue Date
2010-01-12 ’091 Patent Issue Date
2022-01-30 Plaintiff provides actual notice to NXP
2022-11-23 Complaint Filing Date
2024-02-16 Disclaimer of claims 17-20 of the '330 Patent
2024-02-18 Disclaimer of claims 7 and 9-12 of the '245 Patent

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,345,245 - Robust High Density Substrate Design for Thermal Cycling Reliability

Issued March 18, 2008

The Invention Explained

  • Problem Addressed: The patent addresses the problem of functional failures in high-density semiconductor packages caused by thermal stress (Compl. ¶22). In packages using thin core substrates, the areas under the corners of a semiconductor die experience high stress concentration during thermal cycling, which can cause cracks to form at the edges of ball pads and propagate into the overlying signal trace layers ('245 Patent, col. 1:17-27).
  • The Patented Solution: The invention proposes a specific layout rule to improve reliability. It teaches routing signal traces away from a defined "high stress area" located under the die corner to prevent cracks from affecting the traces (Compl. ¶23). The solution is to design the package such that signal traces on a bottom routing layer are not placed directly over ball pads that fall within a specific zone, defined as two ball pad pitches from the die corner ('245 Patent, col. 4:37-58).
  • Technical Importance: This design methodology aims to enhance package reliability and prevent failures from thermal cycling without requiring a reduction in overall signal routing density across the substrate (Compl. ¶25).

Key Claims at a Glance

  • The complaint quotes independent claim 1 and alleges infringement of one or more claims (Compl. ¶¶24, 41).
  • Essential elements of independent claim 1 include:
    • A semi-conductor package comprising a top layer with a die mounted thereon, the die having a corner.
    • A plurality of layers under the top layer, which includes a bottom routing layer with signal traces and a ball pad layer underneath it with a plurality of ball pads.
    • A "keep-out" zone limitation, wherein "none of the signal traces of the bottom routing layer are located over ball pads of the ball pad layer which are disposed in an area within two ball pad pitches of the corner of the die."
  • The complaint alleges infringement of "one or more claims," which could include dependent claims (Compl. ¶41).

U.S. Patent No. 7,535,330 - Low Mutual Inductance Matched Inductors

Issued May 19, 2009

The Invention Explained

  • Problem Addressed: As component density in semiconductors increases, inductors placed in close proximity can interfere with each other through parasitic mutual inductance, where the magnetic field of one inductor degrades the performance of the other (Compl. ¶28). This forces designers to space inductors farther apart, which runs counter to the goal of miniaturization and density ('330 Patent, col. 1:26-34).
  • The Patented Solution: The patent describes a multi-inductor array where two inductor coils are coupled to a common node but are wound in opposite directions (e.g., one clockwise, the other counter-clockwise) (Compl. ¶29). This arrangement generates opposing magnetic fields that at least partially cancel each other out at an "interference point," thereby reducing the problematic mutual inductance ('330 Patent, Abstract; col. 4:8-20).
  • Technical Importance: This technique allows inductors to be placed closer together without performance degradation, enabling higher component density and more efficient use of silicon area in high-speed circuits (Compl. ¶31).

Key Claims at a Glance

  • The complaint quotes independent claim 1 and alleges infringement of one or more claims (Compl. ¶¶30, 51).
  • Essential elements of independent claim 1 include:
    • A multiple inductor array with a first node receiving two currents.
    • A first inductor coil coupled to the first node that communicates the first current in a "clockwise direction" to generate a first magnetic field.
    • A second inductor coil coupled to the first node that communicates the second current in a "counter clockwise direction" to generate a second magnetic field with an "opposing orientation" to the first.
    • A functional requirement that the first and second magnetic fields "at least partially cancel at an interference point."
  • The complaint alleges infringement of "one or more claims," which could include dependent claims (Compl. ¶51).

U.S. Patent No. 7,646,091 - Semiconductor Package and Method Using Isolated Vss Plane to Accommodate High Speed Circuitry Ground Isolation

Issued January 12, 2010

  • Patent Identification: U.S. Patent No. 7,646,091, Semiconductor Package and Method Using Isolated Vss Plane to Accommodate High Speed Circuitry Ground Isolation, issued January 12, 2010 (Compl. ¶32).
  • Technology Synopsis: The patent addresses noise interference in modern integrated circuits that contain both high-speed and low-speed circuitry (Compl. ¶34). To prevent noise from the high-speed circuits from disrupting the low-speed circuits through a shared ground, the invention teaches the use of two electrically isolated ground planes: one dedicated to the high-speed circuitry and another for the low-speed circuitry (Compl. ¶35).
  • Asserted Claims: The complaint quotes independent claim 1 and alleges infringement of "one or more claims" (Compl. ¶¶36, 61).
  • Accused Features: The complaint accuses the NXP LX2160XN72029B Processor of infringing by allegedly incorporating a package structure with separate, isolated ground planes for high-speed and low-speed circuitry (Compl. ¶¶61, 84).

III. The Accused Instrumentality

Product Identification

The complaint identifies specific NXP products, including the MIMX8QP6AVUFFAB Microprocessor, 9SR100 SoC, R10B1AA UWB Transceiver, and LX2160XN72029B Processor, as the "NXP Accused Products" (Compl. ¶1). It also accuses downstream products from other defendants that incorporate these NXP components, such as the Thor96 Board and MSC SM2S-IMX8 SMARC module (Compl. ¶¶69, 74).

Functionality and Market Context

The accused products are semiconductor chips and packages that form the core of various electronic devices, including computers, networking equipment, IoT devices, and automotive systems (Compl. ¶¶1, 18). The infringement allegations are not directed at the products' end-user functions but at their fundamental physical micro-architecture, such as the layout of signal traces, inductors, and ground planes within the silicon and packaging (Compl. ¶¶23, 29, 35). The complaint positions these products as components in a wide array of commercially significant high-tech goods (Compl. ¶18).

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits that were not provided. The following summarizes the infringement theories in prose. No probative visual evidence provided in complaint.

'245 Patent Infringement Allegations

The complaint alleges that the NXP MIMX8QP6AVUFFAB Microprocessor and related products in the i.MX 8M family directly infringe the '245 patent (Compl. ¶41). The theory of infringement is that the physical construction of these packages embodies the limitations of claim 1. Specifically, it is alleged that the packages contain a multi-layer substrate where, in a defined area "within two ball pad pitches of the corner of the die," signal traces on a bottom routing layer are intentionally kept from being routed over the underlying ball pads to enhance thermal reliability (Compl. ¶¶23-24).

'330 Patent Infringement Allegations

The complaint alleges that the NXP 9SR100 SoC and products containing it directly infringe the '330 patent (Compl. ¶51). The infringement theory centers on the physical layout of inductors within the accused chip. It is alleged that the SoC contains a multiple inductor array where two coils are coupled to a common node and wound in opposite (clockwise and counter-clockwise) directions. This structure allegedly generates opposing magnetic fields that partially cancel, thereby meeting the limitations of claim 1 (Compl. ¶¶29-30).

Identified Points of Contention

  • Factual Questions: The core of the dispute for all asserted patents appears to be factual, hinging on the precise physical layout of the accused microprocessors and packages. The case will likely require evidence from reverse engineering or technical discovery to establish whether the accused products' signal traces, inductor windings, and ground planes match the specific structural and geometric requirements of the asserted claims.
  • Scope Questions: For the '245 patent, a key issue may be the precise definition of the "area within two ball pad pitches of the corner of the die." The method of measuring this zone and what constitutes a "pitch" could be points of dispute. For the '330 patent, the construction of "at least partially cancel" may be contested, raising the question of how much magnetic field cancellation is required to meet the claim limitation.

V. Key Claim Terms for Construction

For the '245 Patent

  • The Term: "an area within two ball pad pitches of the corner of the die" (Claim 1).
  • Context and Importance: This phrase defines the geographic "keep-out zone" that is fundamental to the claimed invention. Infringement hinges on whether NXP's products adhere to this specific spatial constraint. Practitioners may focus on this term because its construction will determine the size and shape of the area that must be free of certain signal traces.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the high stress zone as extending "approximately two ball pitches away from the die corner...in each direction," which could support a construction of a generally square or rectangular area ('245 Patent, col. 4:24-28).
    • Evidence for a Narrower Interpretation: Figure 4 of the patent illustrates a specific, somewhat diamond-shaped "high stress zone 58." A party could argue that the claim term should be limited by this specific embodiment, rather than covering any arbitrary area defined by a two-pitch measurement ('245 Patent, Fig. 4).

For the '330 Patent

  • The Term: "at least partially cancel at an interference point" (Claim 1).
  • Context and Importance: This functional language defines the required outcome of the claimed inductor arrangement. The viability of the infringement claim depends on whether the accused devices achieve this effect, and to what degree. Practitioners may focus on this term because its interpretation could set a quantitative or qualitative threshold for infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract states the opposing fields result in "at least a partial cancellation," and the complaint paraphrases the patent as causing a "net reduction in parasitic mutual inductance" (Compl. ¶29). This language could support an argument that any measurable degree of cancellation, however small, satisfies the limitation ('330 Patent, Abstract).
    • Evidence for a Narrower Interpretation: A party could argue that "at least partially" implies a meaningful or substantial degree of cancellation is required, not a de minimis or trivial one. The term "interference point" might also be challenged as indefinite if a specific, identifiable location of cancellation cannot be demonstrated in the accused device.

VI. Other Allegations

Indirect Infringement

The complaint's formal counts focus on direct infringement under 35 U.S.C. § 271(a) (Compl. ¶¶41, 51, 61). However, it lays a potential foundation for indirect infringement claims against the "Downstream Defendants" (Advantech, Arrow, Avnet) by alleging they infringe by "incorporating" the accused NXP products into their own branded products (Compl. ¶¶12, 69).

Willful Infringement

The complaint alleges willful infringement against NXP based on its alleged knowledge of the patents and infringement contentions following "actual notice" provided by a Bell Semiconductor representative on January 30, 2022 (Compl. ¶¶44, 54, 64). For the downstream defendants, willfulness is alleged to have begun "at least as of the date of the Complaint" (e.g., Compl. ¶70).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of factual verification: do the physical micro-architectures of NXP's accused chips—specifically, their signal trace routings, inductor windings, and ground plane layouts—actually conform to the precise geometric and structural limitations recited in the asserted claims? The outcome will likely depend on detailed evidence obtained through discovery and technical analysis.
  • The case will also turn on claim construction, particularly of quantitative and functional terms. Key questions for the court will be defining the precise scope of the "area within two ball pad pitches" in the '245 patent and the required threshold for the "at least partial[] cancel[lation]" of magnetic fields in the '330 patent.
  • A third critical issue involves damages and willfulness, which hinges on the alleged pre-suit notice provided to NXP in January 2022. The timing and sufficiency of this notice will be a focal point in determining the period for which damages may be calculated and whether those damages may be enhanced.