DCT
8:22-cv-02312
Longitude Licensing Ltd v. Dell Tech Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Limited (Ireland)
- Defendant: Dell Technologies, Inc. and Dell, Inc. (Delaware)
- Plaintiff’s Counsel: Russ, August & Kabat
- Case Identification: 8:22-cv-02312, C.D. Cal., 12/23/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendants conduct regular business and maintain a regular and established place of business within the Central District of California.
- Core Dispute: Plaintiff alleges that Dell’s computers, laptops, and tablets that incorporate certain Western Digital solid-state drives (SSDs) and memory chips infringe three U.S. patents related to semiconductor memory system architecture, output buffer circuits, and 3D memory device structure.
- Technical Context: The technology at issue involves high-speed data transfer protocols and the physical design of components within modern solid-state drives, which are fundamental to the performance of contemporary computing devices.
- Key Procedural History: The complaint alleges that Longitude has licensed the patents-in-suit to a majority of the memory industry, but that Western Digital, a component supplier for Defendant Dell, has refused to take a license. Plaintiff states it provided a notice of infringement letter to Dell on September 6, 2022. Subsequent to the filing of this complaint, two of the patents-in-suit became subject to Inter Partes Review (IPR) proceedings at the U.S. Patent and Trademark Office. In IPR2023-01200, asserted claim 1 of the '369 patent was canceled. In IPR2023-01286, asserted claim 1 of the RE43,539 patent was disclaimed by the patent owner.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-16 | '539 Patent Priority Date |
| 2006-06-08 | '369 Patent Priority Date |
| 2007-04-13 | '369 Patent Issued |
| 2012-07-24 | '539 Patent (Reissue) Issued |
| 2014-04-02 | ONFI Standard Revision 4.0 Published |
| 2015-10-01 | '233 Patent Filing Date |
| 2016-06-28 | '233 Patent Issued |
| 2022-09-06 | Plaintiff's Notice of Infringement to Defendants |
| 2022-12-23 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,697,369 - "System with Controller and Memory," issued April 13, 2010
The Invention Explained
- Problem Addressed: The patent describes conventional memory systems where data signals are synchronized with a main clock signal, which can create complexity and require the memory device itself to generate timing signals from that clock (U.S. 7,697,369, col. 1:7-22).
- The Patented Solution: The invention proposes a system where the controller, not the memory, generates data strobe signals for both write and read operations, independent of the main system clock. In a write operation, the controller sends a write strobe signal along with the data. In a read operation, the controller sends a read strobe signal, and the memory responds by sending back both the requested data and a corresponding read data strobe signal. This decouples the data transfer timing from the system clock (U.S. 7,697,369, Abstract; col. 1:28-42).
- Technical Importance: This architecture simplifies the memory device's internal logic by centralizing timing control in the controller and allows the data interface to operate at a different frequency from the main system clock (U.S. 7,697,369, col. 3:36-44).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶30).
- Claim 1 requires a system with:
- A controller adapted to send a first data strobe signal and a synchronized write data signal in a write operation.
- The controller is also adapted to send a second data strobe signal and to receive a read data signal synchronized with a read data strobe signal in a read operation.
- A memory adapted to receive the write data signal synchronized with the first data strobe signal.
- The memory is also adapted to output the read data strobe signal in response to the second data strobe signal and to send the read data signal synchronized with that read data strobe signal.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. RE43,539 - "Output Buffer Circuit and Integrated Semiconductor Circuit Device With Such Output Buffer Circuit," issued July 24, 2012
The Invention Explained
- Problem Addressed: The patent notes that in high-speed, low-voltage semiconductor devices, it is difficult to maintain signal integrity. Variations in temperature and power supply can alter an output signal's timing (cross-point) and rise/fall speed (slew rate), and adjusting these characteristics independently is often ineffective (RE43,539 Patent, col. 1:11-25; col. 2:1-11).
- The Patented Solution: The invention discloses an output buffer with a main driver and a predriver. The circuit is designed with multiple sets of transistors that can be selectively activated by the same control signals to simultaneously adjust both the output impedance and the slew rate. This allows for coordinated control over the output signal's characteristics to compensate for operational variations ('539 Patent, Abstract; col. 3:15-30).
- Technical Importance: This method of unified control over both output impedance and slew rate provides a more robust way to maintain signal integrity in high-speed digital systems, reducing errors caused by environmental fluctuations ('539 Patent, col. 4:18-24).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶57).
- Claim 1 requires an output buffer circuit with:
- A main driver with first and second pairs of p-channel and n-channel MOS transistors.
- A predriver with outputs for driving only the first p-channel and only the first n-channel transistors of the main driver.
- The predriver includes specific third and fourth pairs of transistors for driving the main driver's first transistors.
- The predriver also includes at least one "fifth" n-channel transistor and one "fifth" p-channel transistor that work in "coaction" with the third and fourth pairs, respectively.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
Multi-Patent Capsule: U.S. Patent No. 9,379,233
- Patent Identification: U.S. Patent No. 9,379,233, "Semiconductor Device," issued June 28, 2016.
- Technology Synopsis: This patent addresses inconsistent performance in 3D vertical NAND flash memory. It teaches a specific physical layout where vertical semiconductor pillars are "uniformly arranged" near a shared lower contact plug, which serves to equalize electrical resistance and thereby stabilize the operating characteristics of the individual transistor cells ('233 Patent, Abstract; col. 2:35-51).
- Asserted Claims: The complaint alleges infringement of the '233 patent, implying assertion of at least one claim, likely independent claim 1 based on the complaint's structure (Compl. ¶91, ¶111).
- Accused Features: The accused features are the physical structures of the SanDisk memory chips within the accused Dell products, specifically the layout of the semiconductor pillars, channel regions, gate electrodes, and diffusion layers relative to a contact plug (Compl. ¶99-104).
III. The Accused Instrumentality
- Product Identification: The complaint names Dell computers, laptops, and tablets, with a specific, non-limiting example being the Dell Inspiron 16 computer (model 7620) (Compl. ¶29, ¶56). The core accused components within these devices are identified as the Western Digital PC SN530 NVMe Solid State Drive (SSD) and the SanDisk memory chips contained therein (Compl. ¶31, ¶99).
- Functionality and Market Context: The complaint alleges the accused Western Digital SSD operates in compliance with the Open NAND Flash Interface (ONFI) Specification, Revision 4.0, which defines the communication protocol between a memory controller and NAND flash memory (Compl. ¶32). The infringement allegations for the '369 patent are based on this operational standard. The allegations for the '539 and '233 patents are based on the physical circuit design and semiconductor layout of the SSD's components, which the complaint alleges are key to the product's function (Compl. ¶63-64, ¶98-99). The complaint does not contain specific allegations regarding the products' market positioning beyond their inclusion in Dell's consumer electronics.
IV. Analysis of Infringement Allegations
'369 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a controller adapted to send out a first data strobe signal and a write data signal in a write operation, the write data signal being synchronized with the first data strobe signal | The controller in the Western Digital PC SN530 NVMe SSD sends a write data signal (DQ) and a first data strobe signal (DQS) in a write operation, with the signals being synchronized per the ONFI standard. The complaint includes a timing diagram from the ONFI standard showing this synchronization. (Compl. p. 10) | ¶35 | col. 1:29-32 |
| [a controller adapted] in a read operation, to send out a second data strobe signal and to receive a read data signal in synchronization with a read data strobe signal | The SSD controller is adapted to send a second data strobe signal (RE_t/RE_c) and receive a read data signal (DQ) that is synchronized with a read data strobe signal (DQS) returned from the memory. (Compl. p. 11) | ¶36 | col. 1:32-35 |
| a memory adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation | The memory chip (a SanDisk 512GB NAND Flash memory) in the SSD is adapted to receive the write data signal synchronized with the first data strobe signal during a write operation. (Compl. p. 12) | ¶39 | col. 1:36-39 |
| [a memory adapted] in the read operation, to output the read data strobe signal in response to the second data strobe signal and to send the read data signal synchronized with the read data strobe signal | The memory chip in the SSD is adapted to output the read data strobe signal (DQS) in response to the second data strobe signal (RE_t/RE_c) from the controller, and sends the read data (DQ) synchronized with that read strobe signal. (Compl. p. 13) | ¶40 | col. 1:39-42 |
- Identified Points of Contention:
- Technical Question: The complaint's infringement theory for the '369 patent is predicated on the accused SSD's compliance with the ONFI industry standard (Compl. ¶32). A central factual question for the court will be whether the accused Western Digital product's actual operation conforms to the ONFI standard in all ways material to the claim limitations.
- Scope Question: The '369 patent claims a "system" comprising a "controller" and a "memory." A question may arise as to whether these terms, as defined in the patent, read directly onto the highly integrated components of a modern NVMe SSD, where controller and memory functions are packaged on a single device.
RE43,539 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| An output buffer circuit...comprising: a main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data... | The accused SSD includes an output buffer circuit containing a "main driver" for outputting data. The complaint presents a circuit diagram, purportedly of the accused device, identifying this component. (Compl. p. 21) | ¶64 | col. 11:55-60 |
| a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor... | The accused SSD's output buffer circuit is alleged to include a predriver whose outputs are "directly connected only to said first p-channel MOS transistor and said first n-channel MOS transistor of said main driver." (Compl. p. 33) | ¶67, ¶75 | col. 12:59-65 |
| [a predriver having]...at least one fifth n-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third n-channel MOS transistor... | The predriver circuit is alleged to contain a fifth n-channel MOS transistor that drives the first p-channel transistor in coaction with the third n-channel transistor. The complaint identifies these transistors in a circuit diagram. (Compl. p. 29) | ¶70 | col. 13:5-9 |
| [a predriver having]...at least one fifth p-channel MOS transistor for driving said first n-channel MOS transistor in coaction with said fourth p-channel MOS transistor... | The predriver circuit is alleged to contain a fifth p-channel MOS transistor that drives the first n-channel transistor in coaction with the fourth p-channel transistor. The complaint identifies these transistors in a circuit diagram. (Compl. p. 29) | ¶71 | col. 13:9-13 |
- Identified Points of Contention:
- Technical Question: The complaint's infringement allegations for the '539 patent rely on technical analysis from a TechInsights report concerning a Toshiba SSD, which is alleged to be "substantially similar" to the accused Western Digital SSD (Compl. ¶60, ¶63). A primary point of contention will be the factual and technical validity of this analogy, as the defendants may argue the products are materially different.
- Scope Question: Claim 1 requires a predriver with outputs for driving "only" the specified transistors. The interpretation of "only" will be critical. It raises the question of whether this term imposes an absolute structural limitation (i.e., no other electrical connection of any kind from the output) or a functional one (i.e., no other component is driven by the output).
V. Key Claim Terms for Construction
For the '369 Patent
- The Term: "synchronized with"
- Context and Importance: This term defines the required timing relationship between data signals (DQ) and strobe signals (DQS/RDQS). The viability of the infringement claim depends on whether the accused SSD's signaling meets the level of synchronization required by the patent. Practitioners may focus on this term to dispute whether the alleged adherence to the ONFI standard satisfies the specific timing relationship taught and claimed in the patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the data signal being synchronized with the data strobe signal in general terms, which could support an interpretation that does not require strict clock-edge alignment but rather a general cause-and-effect timing relationship (U.S. 7,697,369, col. 1:30-32).
- Evidence for a Narrower Interpretation: The detailed timing diagrams, such as Figure 6 and Figure 8, show specific rising and falling edge alignments between the signals. A party could argue these embodiments define the necessary level of synchronization more narrowly ('369 Patent, FIG. 6, 8).
For the RE43,539 Patent
- The Term: "a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor"
- Context and Importance: The negative limitation "only" is central to the scope of claim 1. Infringement hinges on whether the predriver outputs in the accused circuit are exclusively connected as claimed. Practitioners may focus on this term because such negative limitations can create a high bar for infringement if construed strictly.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent lacks an explicit definition of "only." A party could argue the term should be interpreted functionally, meaning the output's primary and intended purpose is to drive the specified transistors, and incidental or non-driving connections do not negate this limitation.
- Evidence for a Narrower Interpretation: The plain meaning of "only" suggests exclusivity. A party could argue that if the predriver output is electrically connected to any other component, regardless of function, this limitation is not met. The complaint's own allegation that the output is "directly connected only" to the specified transistors suggests Plaintiff anticipates this will be a point of dispute (Compl. ¶75).
VI. Other Allegations
- Indirect Infringement: The complaint alleges that Defendants induce infringement by their customers and end-users. The basis for inducement is the allegation that Defendants "encourage their customers and end users to perform infringing methods by the very nature of the products" (Compl. ¶43, ¶78, ¶107).
- Willful Infringement: Plaintiff alleges willful infringement of all three patents. The allegations are based on Defendants having knowledge of the patents and their infringement since at least the date of a notice letter, September 6, 2022. The complaint also asserts that Defendants knew or should have known of the "objectively high likelihood that their actions constitute infringement" (Compl. ¶50, ¶85, ¶114).
VII. Analyst’s Conclusion: Key Questions for the Case
Impact of Post-Filing IPR Proceedings: A threshold issue for the '369 and '539 patents is the legal consequence of the inter partes review proceedings initiated after the complaint was filed. The subsequent cancellation or disclaimer of the specific independent claims asserted in Counts I and II raises the fundamental question of whether these causes of action remain viable.
Evidentiary Foundation of Infringement: For the '539 and '233 patents, a key evidentiary question will be one of technical analogy: can the plaintiff prove that the third-party Toshiba memory components, which form the basis of the complaint's technical analysis, are "substantially the same" as the accused Western Digital components for all purposes relevant to the patent claims? The case for infringement on these patents appears to rest heavily on this contested inference.
Claim Construction of Negative Limitations: For the '539 patent, the infringement analysis will likely turn on a matter of definitional scope: how narrowly will the court construe the term "only" in the phrase "a predriver with outputs for driving only said first...transistor"? The interpretation of this restrictive term could be dispositive of infringement for that patent.