DCT
8:23-cv-00033
Longitude Licensing Ltd v. ASUSTeK Computer Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Limited (Ireland)
- Defendant: ASUSTek Computer, Inc. (Taiwan) and ASUS Computer International, Inc. (California)
- Plaintiff’s Counsel: Russ, August & Kabat
- Case Identification: 8:23-cv-00033, C.D. Cal., 01/09/2023
- Venue Allegations: Venue is alleged to be proper as Defendant ASUS Computer International, Inc. has a regular and established place of business in the district, and ASUSTek is a foreign corporation subject to personal jurisdiction.
- Core Dispute: Plaintiff alleges that Defendants’ computers, laptops, and tablets containing certain Western Digital solid-state drives (SSDs) infringe patents related to memory data signaling protocols and the physical structure of semiconductor circuits.
- Technical Context: The technologies involve methods for synchronizing data transfer in memory systems and the physical architecture of 3D NAND flash memory chips, which are fundamental components in modern high-speed computing and data storage.
- Key Procedural History: The complaint states that Plaintiff has licensed the patents-in-suit to a majority of the worldwide memory industry but that Western Digital, the alleged supplier of the infringing components, refused to license. An arbitration initiated by Plaintiff against Western Digital was reportedly dismissed on jurisdictional grounds prior to this suit. Plaintiff alleges it provided Defendants with notice of infringement on September 6, 2022. Subsequent to the complaint's filing, Inter Partes Review (IPR) proceedings were concluded for two of the asserted patents. For the '369 patent, IPR2023-01200 resulted in the cancellation of all asserted claims. For the '539 patent, IPR2023-01286 resulted in the cancellation of one claim and the disclaimer of all other asserted claims.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-16 | '539 Patent Priority Date |
| 2005-05-17 | Original '547 Patent (reissued as '539) Issue Date |
| 2006-06-08 | '369 Patent Priority Date |
| 2010-04-13 | '369 Patent Issue Date |
| 2011-12-27 | '233 Patent Priority Date |
| 2012-07-24 | '539 Reissue Patent Issue Date |
| 2016-06-28 | '233 Patent Issue Date |
| 2022-09-06 | Plaintiff sends infringement notice letter to Defendants |
| 2023-01-09 | Complaint Filing Date |
| 2025-04-18 | IPR Certificate issues canceling asserted claims of '369 Patent |
| 2025-05-20 | IPR Certificate issues disclaiming asserted claims of '539 Patent |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,697,369 - “System with Controller and Memory”
- Issued: April 13, 2010
The Invention Explained
- Problem Addressed: The patent describes conventional data transfer systems where a memory device must generate data strobe signals that are synchronized with a system clock signal provided by a controller, which introduces design complexity and potential timing issues ('369 Patent, col. 1:5-21).
- The Patented Solution: The invention proposes a system where the controller generates its own data strobe signal for synchronizing data transfers, independent of the main system clock. For a read operation, the controller sends a "second data strobe signal" to the memory, and the memory returns a "read data strobe signal" that is then used by the controller to synchronize the incoming data, decoupling the data interface from the system clock ('369 Patent, Abstract; col. 2:26-42).
- Technical Importance: This architecture offered a more flexible protocol for memory interfaces, allowing data transfer timing to be independent of a fixed, system-wide clock and potentially simplifying memory device design ('369 Patent, col. 5:40-48).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶30).
- The essential elements of independent claim 1 include:
- A controller adapted to send a first data strobe signal and a synchronized write data signal in a write operation.
- The controller is also adapted, in a read operation, to send a second data strobe signal and receive a read data signal synchronized with a read data strobe signal that is returned by the memory in response to the second data strobe signal.
- A memory adapted to receive the synchronized write data and first strobe signal.
- The memory is also adapted, in a read operation, to output the read data strobe signal in response to the second data strobe signal and to send the read data signal synchronized with that read data strobe signal.
U.S. Reissue Patent No. RE43,539 - “Output Buffer Circuit and Integrated Semiconductor Circuit Device With Such Output Buffer Circuit”
- Issued: July 24, 2012
The Invention Explained
- Problem Addressed: In high-speed integrated circuits, variations in operating conditions like voltage and temperature can alter the performance of output buffer circuits, affecting signal timing (cross-point) and quality (slew rate) and potentially causing data errors ('539 Patent, col. 1:11-47).
- The Patented Solution: The patent details an output buffer with a main driver and a predriver. The circuit architecture uses multiple, selectable sets of transistors to simultaneously adjust both the output impedance and the rise/fall time (slew rate) of the output signal. The predriver contains specific transistor arrangements, including transistors acting in "coaction," to precisely control the main driver, thereby maintaining signal integrity across different operating conditions ('539 Patent, col. 3:1-col. 4:4).
- Technical Importance: The described circuit provides a method to actively compensate for performance variations in high-speed digital signaling, a critical factor for ensuring reliable operation in advanced memory systems like DDR-SDRAM ('539 Patent, col. 2:20-33).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶57).
- The essential elements of independent claim 1 (as corrected) include:
- A main driver with a first pair of p-channel and n-channel MOS transistors and a second pair of p-channel and n-channel MOS transistors driving a load in "coaction."
- A predriver with outputs connected only to the first pair of transistors in the main driver.
- The predriver itself includes third and fourth pairs of transistors for driving the first pair of transistors in the main driver.
- The predriver also includes at least one fifth n-channel MOS transistor and at least one fifth p-channel MOS transistor that drive the first p-channel and first n-channel transistors, respectively, in "coaction" with other predriver transistors.
U.S. Patent No. 9,379,233 - “Semiconductor Device”
- Issued: June 28, 2016
- Technology Synopsis: This patent addresses structural challenges in 3D flash memory. The problem is to maintain uniform electrical characteristics across multiple vertical transistors by controlling the physical layout. The patented solution is a device structure where multiple "semiconductor pillars" are "uniformly arranged" near a shared "lower diffusion layer side contact plug" to ensure consistent performance ('233 Patent, Abstract; col. 2:6-21).
- Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶¶92, 99).
- Accused Features: The physical layout of the SanDisk 3D NAND memory chip within the accused Western Digital SSD, specifically its arrangement of semiconductor pillars, diffusion layers, and contact plugs, is alleged to infringe (Compl. ¶¶99-104).
III. The Accused Instrumentality
Product Identification
The complaint names "all Asus VivoBook computers (e.g., model F512DA-RH36), all other Asus computers, laptops, and tablets having Western Digital PC SN530 NVMe SSDs, Western Digital SSDs, and/or Western Digital NAND memory chips" (Compl. ¶¶29, 56, 91).
Functionality and Market Context
The accused products are consumer computing devices. The infringement allegations focus on the technical operation and physical structure of the component Western Digital PC SN530 NVMe SSD. The complaint alleges this SSD's controller and memory operate in compliance with the Open NAND Flash Interface (ONFI) 4.0 standard (Compl. ¶32). The complaint provides a photograph of an exemplary ASUS VivoBook computer and its internal components, highlighting the Western Digital PC SN530 NVMe SSD (Compl. ¶¶30-31, pgs. 7-8). The complaint positions Defendants as downstream sellers incorporating allegedly infringing components manufactured by Western Digital/SanDisk (Compl. ¶16).
IV. Analysis of Infringement Allegations
'369 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a controller adapted to send out a first data strobe signal and a write data signal in a write operation, the write data signal being synchronized with the first data strobe signal | The controller in the Western Digital PC SN530 NVMe SSD is alleged to send out a data strobe signal (DQS) and a write data signal (DQ) in a synchronized manner during a write operation, consistent with the ONFI standard timing diagram depicted in the complaint. | ¶35 | col. 2:26-32 |
| the controller being adapted, in a read operation, to send out a second data strobe signal and to receive a read data signal in synchronization with a read data strobe signal, the read data strobe signal being received...in response to the second...signal | The controller is alleged to send a signal (RE_t/RE_c) to initiate a read operation and subsequently receive a read data signal (DQ) synchronized with a read data strobe signal (DQS) returned from the memory in response. | ¶¶36-37 | col. 2:32-37 |
| a memory adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation | The SanDisk NAND flash memory within the SSD is alleged to receive the write data signal (DQ) in synchronization with the first data strobe signal (DQS) sent by the controller. | ¶39 | col. 2:37-40 |
| the memory being adapted, in the read operation, to output the read data strobe signal in response to the second data strobe signal and to send the read data signal synchronized with the read data strobe signal | The NAND flash memory is alleged to output the read data strobe signal (DQS) and the synchronized read data signal (DQ) in response to the controller's read command. The complaint includes a timing diagram from the ONFI standard to illustrate this operation. | ¶40 | col. 2:40-42 |
Identified Points of Contention
- Post-Filing Developments: The cancellation of asserted claim 1 in IPR proceedings subsequent to the complaint's filing raises the question of whether this infringement count remains viable.
- Functional Questions: The complaint's infringement theory for the read operation relies on mapping the controller's read enable signal (RE_t/RE_c) to the "second data strobe signal" of the claim. A potential point of contention is whether a command signal like RE_t, which instructs the memory to generate and send a new strobe (DQS), is functionally the same as the patent's "second data strobe signal," which the specification suggests is looped back from the controller ('369 Patent, col. 3:32-36).
'539 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data | The accused SSD is alleged to have a main driver in its output buffer circuit containing a pair of p-channel and n-channel transistors for driving a load, as depicted in a circuit diagram from a TechInsights report. | ¶65 | col. 3:1-3 |
| and at least a pair of a second p-channel MOS transistor and a second n-channel MOS transistor for driving said load in coaction with said first...transistors | The main driver allegedly includes a second pair of transistors that operate in "coaction" with the first pair to drive the load. | ¶66 | col. 3:3-7 |
| a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor... | The SSD allegedly includes a predriver whose outputs are connected only to the first pair of transistors in the main driver, as required by the claim. The complaint provides a circuit diagram allegedly showing these connections. | ¶¶67, 75 | col. 3:7-10 |
| [the predriver] having...at least one fifth n-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third n-channel MOS transistor | The predriver allegedly contains a fifth n-channel transistor that drives the first p-channel transistor of the main driver in "coaction" with a third n-channel transistor. | ¶70 | col. 3:17-21 |
Identified Points of Contention
- Post-Filing Developments: The disclaimer of asserted claim 1 in IPR proceedings subsequent to the complaint's filing raises the question of whether this count remains viable.
- Scope Questions: The infringement case for this patent relies heavily on analysis from a third-party "TechInsights Report" to identify the claimed transistor structures (Compl. ¶64). A potential issue is whether the circuits in the accused device, which was designed years after the patent's priority date, perform the specific "coaction" functions described and claimed, or if they operate on different principles despite having a similar collection of transistors. The meaning of "coaction" will be central to this inquiry.
V. Key Claim Terms for Construction
'369 Patent: "read data strobe signal being received by the controller in response to the second data strobe signal"
- Context and Importance: This phrase is the crux of the claimed read operation. Infringement hinges on whether the accused SSD's operation under the ONFI standard, where the controller sends a read enable command and the memory generates a new strobe, fits this language.
- Intrinsic Evidence for a Broader Interpretation: The patent's summary states the controller is adapted "to send out a second data strobe signal and to receive a read data signal" ('369 Patent, col. 2:33-35). This language does not inherently require the signal sent out to be the same one that is received back, potentially allowing for a causal "in response to" relationship where one signal prompts the generation of another.
- Intrinsic Evidence for a Narrower Interpretation: The detailed description states, "In the data read operation, the data strobe signal sent out from the controller 100 loopbacks via an interface section...and is used as a data reception synchronizing signal at the controller 100" ('369 Patent, col. 3:32-36). This language may support an interpretation that the "read data strobe signal" is a direct retransmission or "loopback" of the "second data strobe signal," not a new signal generated by the memory.
'539 Patent: "coaction"
- Context and Importance: This term appears multiple times in claim 1 to describe the functional relationship between different sets of transistors in both the main driver and the predriver. The infringement analysis depends on whether the accused circuits exhibit this specific type of cooperative operation.
- Intrinsic Evidence for a Broader Interpretation: The patent does not provide a standalone definition of "coaction," which may suggest the term should be given its plain and ordinary meaning of acting together. This could cover any circuit where multiple transistors contribute to a common function, such as driving a load.
- Intrinsic Evidence for a Narrower Interpretation: The specification describes how adding certain transistors prevents "through current" and adjusts the slew rate ('539 Patent, col. 8:36-58). A party might argue that "coaction" is not just any joint action, but specifically the functional cooperation described in the embodiments to solve these technical problems, thus supporting a more limited, functional definition.
VI. Other Allegations
- Indirect Infringement: The complaint alleges Defendants induce infringement of all asserted patents by selling the accused ASUS products and "encourage[ing] their customers and end users to perform infringing methods by the very nature of the products" (Compl. ¶¶43, 78, 107).
- Willful Infringement: The complaint alleges willful infringement of all asserted patents, based on Defendants' alleged knowledge since at least the date of the notice letter on September 6, 2022, and their continued alleged infringement thereafter (Compl. ¶¶50, 85, 114).
VII. Analyst’s Conclusion: Key Questions for the Case
- Impact of Post-Filing Events: The central question for the '369 and '539 patents is one of viability: given that the asserted claims of both patents were either cancelled or disclaimed in IPRs concluded after the complaint was filed, can these infringement counts proceed or will they be rendered moot?
- Functional Mapping: For any surviving claims of the '369 patent, a key issue will be one of functional interpretation: does an SSD operating under the ONFI standard, where a memory generates a new read strobe (DQS) after receiving a read enable command, practice the claimed method where a controller receives a read strobe "in response to" a "second data strobe signal" it sends? This turns on the technical definition of a "data strobe signal" versus a command, and the scope of the "in response to" relationship.
- Structural Interpretation: For the '233 patent, the case will likely focus on a question of physical structure: does the layout of the transistors in the accused SanDisk memory chip meet the "uniformly arranged" limitation of claim 1? This will require detailed, evidence-based analysis of the physical semiconductor device and the construction of this key claim term.