DCT
8:23-cv-00035
Longitude Licensing Ltd v. Lenovo Group Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Limited (Ireland)
- Defendant: Lenovo Group, Limited (China); Lenovo (United States), Inc. (Delaware)
- Plaintiff’s Counsel: Russ, August & Kabat
- Case Identification: 8:23-cv-00035, C.D. Cal., 01/09/2023
- Venue Allegations: Plaintiff alleges venue is proper based on Defendants' business transactions and acts of infringement in the district, and on Defendant Lenovo (United States), Inc. maintaining a regular and established place of business in the district, evidenced by job postings and employee residences.
- Core Dispute: Plaintiff alleges that Defendants’ computers, laptops, and tablets incorporating certain Western Digital solid-state drives (SSDs) infringe three patents related to semiconductor memory operation and structure.
- Technical Context: The patents concern technologies for high-speed data transfer protocols and the physical architecture of 3D NAND flash memory, which are foundational technologies for modern data storage devices.
- Key Procedural History: The complaint alleges that Plaintiff provided notice of infringement to Defendants on September 6, 2022, following a prior licensing dispute with the component supplier, Western Digital. Subsequent to the complaint's filing, Inter Partes Review (IPR) proceedings were initiated against the '369 and '539 patents. The U.S. Patent and Trademark Office has since issued certificates indicating that the asserted claims of the '369 patent were cancelled and the asserted claims of the '539 patent were disclaimed.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-16 | ’539 Patent Priority Date |
| 2006-06-08 | ’369 Patent Priority Date |
| 2010-04-13 | ’369 Patent Issue Date |
| 2011-12-27 | ’233 Patent Priority Date |
| 2012-07-24 | ’539 Patent Issue Date |
| 2016-06-28 | ’233 Patent Issue Date |
| 2022-09-06 | Plaintiff sends infringement notice letter to Defendants |
| 2023-01-09 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,697,369 - "System with Controller and Memory," issued April 13, 2010
The Invention Explained
- Problem Addressed: The patent describes conventional data transfer systems where a memory device and controller rely on a shared, synchronized clock signal, which can create system-level dependencies and limit performance flexibility (U.S. Patent No. 7,697,369, col. 1:8-14).
- The Patented Solution: The invention discloses a system where data transfer is managed by a data strobe signal that is independent of the system's clock signal. A controller sends data strobes to initiate write and read operations, and the memory generates and returns a read data strobe signal (RDQS) to synchronize the return of read data, decoupling the data transfer timing from the main clock frequency (’369 Patent, Abstract; col. 2:25-42).
- Technical Importance: This protocol allows the data transfer interface to operate at frequencies different from the main system clock, enabling more flexible and potentially higher-speed communication between a controller and memory (’369 Patent, col. 6:39-44).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶30).
- Essential elements of claim 1 include:
- A controller that sends a first data strobe and a synchronized write data signal in a write operation.
- The controller, in a read operation, sends a second data strobe and receives a read data signal synchronized with a read data strobe signal it receives from the memory.
- A memory that receives the write data signal synchronized with the first data strobe.
- The memory, in a read operation, outputs the read data strobe signal in response to the second data strobe signal and sends the read data signal synchronized with that read data strobe signal.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Reissue Patent No. RE43,539 - "Output Buffer Circuit and Integrated Semiconductor Circuit Device With Such Output Buffer Circuit," issued July 24, 2012
The Invention Explained
- Problem Addressed: High-speed integrated circuits suffer from variations in signal timing (cross-point) and rise/fall times (slew rate) due to fluctuations in power supply voltage and temperature, which can lead to data errors (’539 Patent, col. 1:49-55).
- The Patented Solution: The patent describes an output buffer with a main driver and a predriver. The predriver contains multiple, selectable sets of transistors that are used to drive the main driver's transistors. By activating different combinations of these predriver transistors, the circuit can simultaneously adjust both the output impedance and the slew rate, allowing for more precise control and compensation for operational variances (’539 Patent, Abstract; col. 3:15-24).
- Technical Importance: This design provides a mechanism for robust high-speed signaling in memory devices by enabling dynamic compensation for variables that could otherwise compromise signal integrity.
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶57).
- Essential elements of claim 1 include a complex arrangement of transistors within an output buffer circuit:
- A main driver with a first pair of p-channel and n-channel MOS transistors.
- A second pair of p-channel and n-channel MOS transistors driving the load in "coaction" with the first pair.
- A predriver with outputs for driving "only" the first p-channel and first n-channel transistors of the main driver.
- The predriver itself contains specific pairs of third and fourth p-channel and n-channel transistors for driving the main driver's transistors, as well as a fifth n-channel transistor for driving the first p-channel transistor in "coaction" with the third n-channel transistor.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 9,379,233 - "Semiconductor Device," issued June 28, 2016
- Patent Identification: U.S. Patent No. 9,379,233, "Semiconductor Device," issued June 28, 2016 (Compl. ¶87).
- Technology Synopsis: The patent addresses the challenge of maintaining stable electrical characteristics in vertical transistor arrays used in 3D NAND memory. The invention proposes a physical layout where vertical semiconductor pillars are uniformly arranged near a shared lower diffusion layer contact plug. This uniform spacing is intended to equalize parasitic resistance from the contact plug to each pillar, thereby stabilizing the performance across the array of transistors (’233 Patent, col. 2:9-21).
- Asserted Claims: The complaint asserts at least claim 1 of the ’233 patent (Compl. ¶91, ¶92).
- Accused Features: The SanDisk memory chip within the Western Digital SSD is accused of infringing. The complaint alleges the chip’s physical structure, including its plurality of semiconductor pillars, semiconductor substrate, lower diffusion layer, and side contact plug, embodies the claimed invention (Compl. ¶¶99-104).
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are Lenovo computers, laptops, and tablets, such as the Lenovo IdeaPad 3 (e.g., model 81X800L0CF), that contain Western Digital PC SN530 NVMe SSDs, Western Digital SSDs, and/or Western Digital 3D NAND memory chips (Compl. ¶29, ¶56, ¶91).
Functionality and Market Context
The complaint focuses on the technical operation of the Western Digital PC SN530 NVMe SSD component within Lenovo's products. For the ’369 patent, the relevant functionality is the SSD's data transfer protocol, which allegedly complies with the Open NAND Flash Interface (ONFI) Specification (Compl. ¶32). For the ’539 and ’233 patents, the relevant functionality and structure are those of the output buffer circuits and physical memory die architecture within the SanDisk-branded NAND flash memory chips used in the SSD (Compl. ¶63, ¶98). The complaint alleges these components are integral to the function of the accused Lenovo products. A photo shows the internal components of a Lenovo IdeaPad 3, highlighting the location of the Western Digital PC SN530 NVMe SSD (Compl. ¶31, p. 8).
IV. Analysis of Infringement Allegations
’369 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a controller adapted to send out a first data strobe signal and a write data signal in a write operation, the write data signal being synchronized with the first data strobe signal | The SSD's controller sends a DQS (Data Strobe) signal and a DQ (Data) signal, with the data signal being synchronized with the DQS signal during write operations, as shown in an ONFI timing diagram. | ¶35 | col. 7:12-16 |
| the controller being adapted, in a read operation, to send out a second data strobe signal and to receive a read data signal in synchronization with a read data strobe signal | The controller sends a second data strobe signal and receives a read data signal that is synchronized with a read strobe signal, as shown in an ONFI timing diagram for a data output cycle. | ¶36 | col. 7:16-22 |
| the read data strobe signal being received by the controller in response to the second data strobe signal | The controller receives the read strobe signal in response to the second data strobe signal it sent, as depicted in an ONFI timing diagram. | ¶37 | col. 7:20-22 |
| a memory adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation | The SSD's NAND Flash memory receives the write data signal synchronized with the first data strobe signal during a write operation. | ¶39 | col. 7:23-26 |
| the memory being adapted, in the read operation, to output the read data strobe signal in response to the second data strobe signal and to send the read data signal synchronized with the read data strobe signal | The memory outputs the read data strobe signal in response to receiving the second data strobe signal from the controller and sends the read data signal synchronized with this outputted strobe. | ¶40 | col. 7:26-30 |
Identified Points of Contention
- Scope Questions: A central question is whether the signals defined in the ONFI standard (e.g., DQS) are structurally and functionally the same as the "data strobe signal" recited in the patent claims.
- Technical Questions: The infringement theory relies on the allegation that the accused SSD operates in compliance with the ONFI standard (Compl. ¶32). The primary technical question for the court will be whether the actual operation of the accused SSD's controller and memory conforms to the ONFI standard in a way that meets every limitation of claim 1.
’539 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data | The accused SSD's output buffer circuit includes a main driver, which in turn includes a pair of transistors (one p-channel, one n-channel) for driving a load according to data. A circuit diagram from a TechInsights report allegedly depicts this structure. | ¶65 | col. 13:45-49 |
| a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor | The accused SSD includes a predriver whose outputs drive only the first n-channel and first p-channel MOS transistors of the main driver. The complaint alleges this is shown in circuit diagrams. | ¶67 | col. 13:51-53 |
| at least one fifth n-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third n-channel MOS transistor | The accused SSD includes at least one fifth n-channel MOS transistor that drives the first p-channel transistor in coaction with the third n-channel transistor. A circuit diagram allegedly shows this co-action. | ¶70 | col. 13:60-64 |
Identified Points of Contention
- Factual Questions: The infringement allegations for the ’539 Patent are based on a TechInsights report analyzing a Toshiba chip, which the complaint alleges on "information and belief" is "substantially the same" as the accused Western Digital/SanDisk chip (Compl. ¶¶60-63). A threshold issue will be whether Plaintiff can prove this technological equivalence. The complaint includes a side-by-side comparison of the dies of the SanDisk and Toshiba chips to support this assertion (Compl. ¶62, p. 23).
- Scope Questions: The claim uses highly specific language like "driving only," "third p-channel," and "in coaction with." The court will need to construe these terms, and the analysis will require a detailed, transistor-level comparison between the claim language and the accused circuit diagrams. The meaning of "coaction" will be particularly important.
V. Key Claim Terms for Construction
For the ’369 Patent
- The Term: "in response to the second data strobe signal"
- Context and Importance: This term defines the relationship between the controller's strobe signal and the memory's generation of its own read data strobe signal (RDQS). The infringement case depends on showing that the accused memory's action is contingent on the controller's signal in the manner required by the claim.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language could be argued to mean that the memory's output of the RDQS simply occurs during the same read operation that was initiated by the controller's second data strobe signal, not that the signal itself is the direct trigger for RDQS generation.
- Evidence for a Narrower Interpretation: The specification states that the memory "generates the RDQS signal from the data strobe signal in the read operation" (’369 Patent, col. 4:61-63). This language suggests a direct, causal link, where the controller's strobe signal is the input from which the memory's RDQS is generated, supporting a more restrictive interpretation.
For the ’539 Patent
- The Term: "predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor"
- Context and Importance: This "driving only" limitation is highly restrictive and appears central to defining the claimed predriver's structure. Practitioners may focus on this term because if the predriver's outputs connect to any components other than the specified main driver transistors, infringement may be avoided.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party might argue "driving" refers to providing the primary control signal, and the term does not exclude other incidental or non-driving connections.
- Evidence for a Narrower Interpretation: The plain meaning of "only" implies exclusivity. The complaint itself alleges the predriver output is "directly connected only" to the specified transistors, suggesting Plaintiff anticipates a narrow reading (Compl. ¶75). The specific embodiments and figures in the patent (’539 Patent, Fig. 3) will be critical evidence to determine if the inventor intended to exclude all other connections from the predriver's output path.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement, stating that Defendants "encourage their customers and end users to perform infringing methods by the very nature of the products" (Compl. ¶43, ¶78, ¶107).
- Willful Infringement: Willfulness is alleged based on Defendants' continued infringement after receiving actual notice via a letter dated September 6, 2022. The complaint alleges Defendants knew or should have known of the objectively high likelihood of infringement (Compl. ¶50, ¶85, ¶114).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central procedural question will be one of viability: given that the asserted claims of the '369 and '539 patents were cancelled or disclaimed in IPRs filed after the complaint, can the causes of action based on those patents proceed?
- A key evidentiary issue for the '539 and '233 patents will be one of technological identity: can Plaintiff meet its burden to prove that the accused Western Digital/SanDisk memory chips are structurally and functionally equivalent to the third-party Toshiba products analyzed in the reports upon which the infringement allegations rely?
- A critical legal and technical question for the '369 patent will be one of functional mapping: does the operation of the accused SSD under the ONFI standard, particularly its use of the DQS signal, meet the specific sequence of operations recited in claim 1, including the memory outputting a read data strobe "in response to" the controller's strobe?