DCT
8:23-cv-00036
Longitude Licensing Ltd v. Acer Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Limited (Ireland)
- Defendant: Acer, Inc. (Taiwan); Acer America Corp. (California)
- Plaintiff’s Counsel: Russ, August & Kabat
- Case Identification: 8:23-cv-00036, C.D. Cal., 01/09/2023
- Venue Allegations: Plaintiff alleges venue is proper in the Central District of California because Defendants transact business and have committed acts of infringement in the district, and because Defendant Acer America has employees who reside there.
- Core Dispute: Plaintiff alleges that Defendant’s computers, laptops, and tablets containing solid-state drives (SSDs) with Western Digital components infringe patents related to semiconductor memory operation and structure.
- Technical Context: The lawsuit concerns technologies fundamental to modern data storage, including high-speed data transfer protocols, output buffer circuit design, and the physical architecture of 3D NAND flash memory.
- Key Procedural History: The complaint states that Plaintiff has licensed the patents-in-suit to a majority of the memory industry but that a key component supplier, Western Digital, has refused to take a license. Subsequent to the filing of this complaint, the asserted independent claims of the '369 and '539 patents have been affected by Inter Partes Review (IPR) proceedings. The asserted independent claim 1 of the '369 patent was cancelled. The asserted independent claim 1 of the '539 patent was disclaimed by the patent owner. The complaint alleges Defendants had pre-suit notice via a letter dated September 6, 2022.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-16 | '539 Patent Priority Date |
| 2006-06-08 | '369 Patent Priority Date |
| 2010-04-13 | '369 Patent Issue Date |
| 2011-12-27 | '233 Patent Priority Date |
| 2012-07-24 | '539 Patent Reissue Date |
| 2016-06-28 | '233 Patent Issue Date |
| 2022-09-06 | Plaintiff sends notice letter to Defendants |
| 2023-01-09 | Complaint Filing Date |
| 2023-07-14 | IPR (IPR2023-01200) filed against '369 Patent |
| 2023-08-08 | IPR (IPR2023-01286) filed against '539 Patent |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,697,369 - "System with Controller and Memory" (issued Apr. 13, 2010)
The Invention Explained
- Problem Addressed: The patent describes conventional data transfer systems between a controller and a memory as being synchronized to a clock signal, which creates rigid dependencies and can limit performance and flexibility. (’369 Patent, col. 1:7-22).
- The Patented Solution: The invention proposes a protocol where the controller generates a "data strobe signal" that is independent of the system's primary "clock signal". This strobe signal, not the clock, is used to synchronize the sending and receiving of data. The controller issues a first strobe for write operations and a second for read operations, and the memory generates a corresponding read data strobe signal for returning data, allowing the data transfer frequency to operate independently of the main system clock. (’369 Patent, Abstract; col. 2:26-42).
- Technical Importance: Decoupling the data bus from the system clock allows for more flexible memory system designs, enabling the use of memory components with different speed capabilities and optimizing data transfer rates. (’369 Patent, col. 6:33-40).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶30).
- Essential elements of claim 1 include:
- A system with a controller and a memory.
- The controller sends a first data strobe and a synchronized write data signal during a write operation.
- The controller sends a second data strobe during a read operation and receives a read data signal synchronized with a read data strobe signal.
- The memory receives the write data signal synchronized with the first data strobe.
- The memory, in a read operation, outputs the read data strobe signal in response to the second data strobe and sends the read data signal synchronized with that read data strobe signal.
U.S. Reissue Patent No. RE43,539 - "Output Buffer Circuit and Integrated Semiconductor Circuit Device With Such Output Buffer Circuit" (issued Jul. 24, 2012)
The Invention Explained
- Problem Addressed: High-speed integrated circuits are susceptible to performance variations caused by fluctuations in power supply voltage, ambient temperature, and manufacturing processes. These variations can alter an output buffer's impedance and slew rate (signal rise/fall time), degrading signal integrity. (’539 Patent, col. 1:21-44).
- The Patented Solution: The patent discloses an output buffer circuit with a main driver and a predriver architected to simultaneously control both output impedance and slew rate. This is accomplished by using multiple sets of transistors that can be selectively activated to adjust the driving strength for both rising and falling signal edges, thereby compensating for external and internal variations. (’539 Patent, Abstract; col. 3:1-12). Figure 3 illustrates the interconnected main driver, predriver, and controller.
- Technical Importance: This method of simultaneous control provides more robust and reliable high-speed signaling, which is critical for data-intensive applications like DDR-SDRAM to ensure data is transmitted and received without errors. (’539 Patent, col. 2:54-61).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶57).
- Essential elements of claim 1 (as corrected) include:
- An output buffer circuit for outputting data at a predetermined impedance and slew rate.
- A "main driver" with a first pair of p-channel and n-channel MOS transistors and a second pair that drives a load "in coaction with" the first pair.
- A "predriver" with outputs for driving only the first n-channel and first p-channel MOS transistors of the main driver.
- The predriver contains specific third and fourth pairs of transistors for driving the first p-channel and first n-channel transistors of the main driver, respectively.
- The predriver also contains a fifth n-channel transistor and a fifth p-channel transistor that act "in coaction with" the third and fourth pairs.
U.S. Patent No. 9,379,233 - "Semiconductor Device" (issued June 28, 2016)
The Invention Explained
- Technology Synopsis: The patent addresses challenges in creating high-density 3D NAND flash memory. It describes a structure with multiple vertical semiconductor pillars that serve as transistor channels, which are uniformly arranged around a shared conductive contact plug connected to a lower diffusion layer (’233) Patent, Abstract; col. 2:10-20). This uniform arrangement is intended to stabilize transistor characteristics across the device, a critical factor for reliable operation in densely packed memory chips (’233 Patent, col. 1:50-56).
Key Claims at a Glance
- Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶92).
- Accused Features: The accused feature is the physical 3D NAND architecture of the SanDisk memory chip inside the accused SSD. The complaint points to micrographs allegedly showing a plurality of semiconductor pillars, a shared lower diffusion layer, and a side contact plug, which are asserted to map to the claim elements (Compl. ¶99-104). This is supported by a visual from a technical analysis showing a cross-section of the memory chip's structure (Compl. p. 44).
III. The Accused Instrumentality
Product Identification
The complaint names Acer Aspire 5 and Nitro 5 computers, as well as other Acer laptops and tablets that incorporate Western Digital PC SN530 NVMe SSDs, other Western Digital SSDs, or Western Digital NAND memory chips (Compl. ¶29, 56). The Acer Aspire 5 (model A515-56-74PH) is identified as a representative infringing product (Compl. ¶30).
Functionality and Market Context
The infringement allegations center on the components and operation of the Western Digital PC SN530 NVMe SSD contained within Acer's products. For the '369 patent, the accused functionality is the data transfer protocol between the SSD's controller and its NAND flash memory, which allegedly complies with the ONFI 4.0 standard and uses independent data strobes for synchronization (Compl. ¶32, 35, 36). For the '539 and '233 patents, the allegations target the internal circuitry and physical structure of the memory chips themselves, which are fundamental to the SSD's storage function (Compl. ¶64, 99). The complaint provides a photograph of the accused SSD installed inside an Acer laptop. (Compl. p. 8).
IV. Analysis of Infringement Allegations
'369 Patent Infringement Allegations
The complaint alleges that the accused SSD's controller and memory operate according to the ONFI standard, which uses data strobe signals (DQS) to synchronize data (DQ) signals, as depicted in a timing diagram provided in the complaint (Compl. p. 11, Figure 71).
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a controller adapted to send out a first data strobe signal and a write data signal in a write operation, the write data signal being synchronized with the first data strobe signal | The SSD includes a controller that sends a first data strobe signal (DQS) and a synchronized write data signal (DQ) during a write operation, as shown in ONFI standard timing diagrams. | ¶35 | col. 2:28-31 |
| the controller being adapted, in a read operation, to send out a second data strobe signal and to receive a read data signal in synchronization with a read data strobe signal | In a read operation, the controller is adapted to send a second data strobe signal and receive a read data signal (DQ) that is synchronized with a read strobe signal (DQS). | ¶36 | col. 2:32-35 |
| a memory adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation | The SSD includes NAND flash memory that receives the write data signal in synchronization with the first data strobe signal during a write operation. | ¶39 | col. 2:36-39 |
| the memory being adapted, in the read operation, to ... send the read data signal synchronized with the read data strobe signal | In a read operation, the memory is adapted to send the read data signal synchronized with the read data strobe signal, as shown in ONFI standard timing diagrams. | ¶40 | col. 2:39-42 |
- Identified Points of Contention:
- Scope Questions: A central question will be whether the accused SSD's general compliance with the ONFI standard is sufficient to prove that its controller and memory perform the specific sender/receiver roles as defined in the claim. Evidence will be required to show that the "controller" itself is the source of the first and second data strobe signals.
- Technical Questions: What evidence demonstrates that the read data strobe signal received by the controller is generated by the memory "in response to" the second data strobe signal sent from the controller, as opposed to being generated based on an internal memory clock or other stimulus?
'539 Patent Infringement Allegations
The allegations for the '539 patent rely on a third-party technical analysis of a purportedly "substantially similar" Toshiba SSD to identify the claimed circuit structures (Compl. ¶60, 63). The complaint includes a circuit diagram from this analysis allegedly showing the main driver (Compl. p. 23, Figure 4.11).
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a main driver ... comprising a main driver | The accused SSD includes an output buffer circuit with a main driver for outputting data. | ¶64 | col. 4:51-54 |
| at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data | The main driver includes a first pair of p-channel and n-channel MOS transistors for driving a load. | ¶65 | col. 5:2-5 |
| at least a pair of a second p-channel MOS transistor and a second n-channel MOS transistor for driving said load in coaction with said first p-channel MOS transistor and said first n-channel MOS transistor | The main driver includes a second pair of p-channel and n-channel MOS transistors that drive the load in coaction with the first pair. | ¶66 | col. 5:5-9 |
| a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor | The accused device includes a predriver whose outputs are for driving only the first n-channel and first p-channel transistors of the main driver. | ¶67 | col. 5:9-12 |
- Identified Points of Contention:
- Evidentiary Questions: The infringement theory hinges on the assertion that a Toshiba SSD is "substantially similar" to the accused Western Digital SSD. A primary dispute will be whether evidence from this proxy product is sufficient to meet the pleading standard and, later, the burden of proof for infringement.
- Scope Questions: Does the accused circuit's operation meet the "in coaction with" limitation? The interpretation of this term will be critical to determine if the relationship between the primary and secondary sets of transistors in the accused driver falls within the claim's scope.
V. Key Claim Terms for Construction
'369 Patent
- The Term: "controller"
- Context and Importance: The claims require the "controller" to be the active entity that sends strobe signals to initiate and manage data transfers. The complaint identifies the "SanDisk...SSD Controller" as this element (Compl. ¶34). The construction of this term is critical for defining the boundaries of the claimed system and identifying the infringing actor.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the controller in general terms as a "CPU" or other logic that gives instructions to the memory, which may support a functional definition. (’369 Patent, col. 3:9-12).
- Evidence for a Narrower Interpretation: The detailed description provides a specific block diagram for the controller (Figure 2), including a "C/A control circuit," "PLL/DLL," and "data strobe signal generating section." A party could argue that a "controller" must comprise these or equivalent structures. (’369 Patent, col. 3:50-54).
'539 Patent
- The Term: "in coaction with"
- Context and Importance: This term describes the functional relationship between the first and second sets of transistors in the main driver. Practitioners may focus on this term because its definition—whether it implies simultaneous, supplementary, or some other form of coordinated action—will be central to determining if the accused driver, with its multiple transistor stages, operates in an infringing manner.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not explicitly define the term, which may support giving it a plain and ordinary meaning of "acting together" or "in cooperation."
- Evidence for a Narrower Interpretation: The patent’s objective is to control the slew rate and impedance simultaneously (’539 Patent, Abstract). A party could argue that "coaction" requires a specific, coordinated timing relationship between the activation of the first and second transistor pairs to achieve this stated goal, rather than just a cumulative effect.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement for all patents, asserting that Defendants knew of the patents (from at least the notice letter) and intended for their customers to infringe by providing products that, by their nature, perform the infringing functions (Compl. ¶41-44, 76-79, 105-108).
- Willful Infringement: Willfulness allegations are based on Defendants' alleged knowledge of the patents and infringement since at least the date of the September 6, 2022 notice letter, and their continued infringement thereafter (Compl. ¶50, 85, 114).
VII. Analyst’s Conclusion: Key Questions for the Case
- Impact of Post-Filing IPRs: A threshold issue is the viability of the case itself, given that the asserted independent claims of the '369 patent (claim 1) and '539 patent (claim 1) were cancelled and disclaimed, respectively, in IPR proceedings initiated after the complaint was filed. The future of the litigation will depend on whether Plaintiff can proceed on other, unasserted claims.
- Sufficiency of Proxy Evidence: A key evidentiary question will be whether the infringement analysis for the '539 and '233 patents, which is based on a "substantially similar" Toshiba product, is sufficient to establish infringement of the accused Western Digital product.
- Definitional Scope: For the '369 patent, a core issue will be whether the accused system's adherence to the ONFI standard necessarily proves that the "controller" performs the specific signal-sending functions required by the claims, or if the standard allows for an implementation that falls outside the claim's scope.