DCT
8:23-cv-00038
Longitude Licensing Ltd v. HP Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Limited (Ireland)
- Defendant: HP Inc. (Delaware)
- Plaintiff’s Counsel: Russ, August & Kabat
- Case Identification: 8:23-cv-00038, C.D. Cal., 01/09/2023
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is subject to personal jurisdiction, has committed acts of infringement in the district, and maintains a regular and established place of business in the district.
- Core Dispute: Plaintiff alleges that Defendant’s computers, laptops, and tablets incorporating Western Digital solid-state drives (SSDs) infringe patents related to semiconductor memory signaling protocols, output buffer circuit design, and 3D memory device structure.
- Technical Context: The technologies at issue relate to fundamental aspects of semiconductor memory design, including high-speed data transfer interfaces and the physical layout of modern 3D NAND flash memory cells.
- Key Procedural History: The complaint alleges that Plaintiff has licensed the patents-in-suit to a majority of the memory industry, but that Western Digital, the supplier of the accused components in Defendant's products, has refused to take a license. Plaintiff states it sent a notice letter to Defendant regarding the alleged infringement on September 6, 2022. Subsequent to the complaint's filing, Inter Partes Review (IPR) proceedings have resulted in the cancellation or disclaimer of all asserted claims of the '369 and '539 patents.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-16 | U.S. Patent RE43,539 Priority Date |
| 2005-05-17 | Original U.S. Patent 6,894,547 (reissued as '539) Issued |
| 2006-06-08 | U.S. Patent 7,697,369 Priority Date |
| 2010-04-13 | U.S. Patent 7,697,369 Issued |
| 2011-12-27 | U.S. Patent 9,379,233 Priority Date |
| 2012-07-24 | U.S. Patent RE43,539 Reissued |
| 2016-06-28 | U.S. Patent 9,379,233 Issued |
| 2018-02-01 | Plaintiff allegedly began license negotiations with Western Digital |
| 2022-09-06 | Plaintiff sent notice letter to Defendant |
| 2023-01-09 | Complaint Filed |
| 2025-04-18 | IPR Certificate issues cancelling asserted claims of '369 Patent |
| 2025-05-20 | IPR Certificate issues disclaiming asserted claims of '539 Patent |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent 7,697,369 - System with Controller and Memory (Issued Apr. 13, 2010)
The Invention Explained
- Problem Addressed: The patent describes conventional memory systems where data transfer signals are synchronized with a system clock signal, which can create design complexity, particularly for the memory device which must generate its own read data strobe signal from that clock ('369 Patent, col. 1:8-21).
- The Patented Solution: The invention proposes a system where the data strobe signal used for timing data transfers is generated by the controller and is independent of the main system clock signal ('369 Patent, Abstract). In a write operation, the controller sends a data strobe with the data; in a read operation, the memory receives a data strobe from the controller and sends back a read data strobe signal in response, which it uses to time the outgoing read data ('369 Patent, col. 1:26-42). This decoupling simplifies the memory's internal timing logic.
- Technical Importance: This architecture allows a single controller to more flexibly manage different types of memory (e.g., high-speed and low-speed) that may operate with different data rates, as the data timing is not rigidly tied to a single, fixed-frequency clock ('369 Patent, col. 5:39-49).
Key Claims at a Glance
- The complaint asserts independent claim 1 ('369 Patent, IPR Certificate, p. 2). Note: This claim has been cancelled in an IPR proceeding.
- Key elements of the cancelled claim 1 include:
- A system with a controller and a memory.
- The controller sends a first data strobe signal and a synchronized write data signal.
- The controller sends a second data strobe signal and receives a read data signal synchronized with a read data strobe signal.
- The memory receives the write data signal synchronized with the first data strobe.
- The memory outputs the read data strobe signal "in response to the second data strobe signal" and sends the read data synchronized with that read data strobe signal.
- The complaint reserves the right to assert other claims (Compl. ¶28).
U.S. Reissue Patent RE43,539 - Output Buffer Circuit and Integrated Semiconductor Circuit Device With Such Output Buffer Circuit (Issued Jul. 24, 2012)
The Invention Explained
- Problem Addressed: High-speed semiconductor circuits suffer from variations in output signal timing caused by fluctuations in power supply voltage and temperature. These variations affect the "slew rate" (signal transition speed) and the "cross-point" (voltage at which rising and falling signals intersect), which can lead to data errors ('539 Patent, col. 1:28-47).
- The Patented Solution: The patent describes an output buffer with a "main driver" to send the signal and a "predriver" to control it. The predriver contains multiple sets of transistors that can be selectively activated to adjust the main driver's performance. This allows for simultaneous control over both the output impedance and the slew rate, stabilizing the signal's timing characteristics ('539 Patent, Abstract; col. 3:1-12).
- Technical Importance: This technique provides a method for maintaining high signal integrity in memory interfaces despite process, voltage, and temperature (PVT) variations, a critical requirement for reliable operation in technologies like DDR SDRAM ('539 Patent, col. 2:46-51).
Key Claims at a Glance
- The complaint asserts independent claim 1 ('539 Patent, IPR Certificate, p. 2). Note: This claim has been disclaimed in an IPR proceeding.
- Key elements of the disclaimed claim 1 include:
- An output buffer circuit comprising a main driver and a predriver.
- The main driver has a first pair of p-channel and n-channel MOS transistors.
- The predriver has outputs for driving "only" the first p-channel and "only" the first n-channel transistors of the main driver.
- The predriver includes specific pairs of third and fourth p-channel/n-channel transistors for driving the main driver's transistors.
- The predriver includes specific "fifth" coacting transistors to further adjust the driving characteristics.
- The complaint reserves the right to assert other claims (Compl. ¶55).
U.S. Patent 9,379,233 - Semiconductor Device (Issued June 28, 2016)
- Patent Identification: U.S. Patent 9,379,233, "Semiconductor Device," issued June 28, 2016 (Compl. ¶86).
- Technology Synopsis: The technology relates to the physical structure of 3D NAND flash memory. It addresses the problem where non-uniform spacing between vertical memory cell "pillars" and a shared electrical "contact plug" causes inconsistent performance among the transistors. The patented solution is a device structure where the pillars are "uniformly arranged" around the contact plug, defined such that the maximum pillar-to-plug distance is no more than twice the minimum distance, thereby stabilizing the electrical characteristics ('233 Patent, Abstract; col. 2:3-9, 45-51).
- Asserted Claims: At least claim 1 is asserted (Compl. ¶¶91, 98).
- Accused Features: The complaint alleges that the physical structure of the SanDisk 3D NAND memory chip, as shown in micrographs, infringes by having a plurality of semiconductor pillars uniformly arranged around a lower diffusion layer side contact plug (Compl. ¶¶98, 102). A micrograph shows the accused arrangement of semiconductor pillars (Compl. ¶98, p. 44).
III. The Accused Instrumentality
Product Identification
- The complaint identifies HP computers, laptops, and tablets, with the HP Laptop model 15-dy2033nr cited as a specific example (Compl. ¶¶28, 29). The infringement allegations focus on components within these products, namely the Western Digital PC SN530 NVMe Solid State Drive (SSD) and the SanDisk-branded NAND flash memory chips contained therein (Compl. ¶¶30, 37, 57).
Functionality and Market Context
- The accused instrumentalities are mass-market consumer electronic devices (Compl. ¶17). The core of the infringement allegations relates to the technical operation of the memory subsystems within them.
- For the '369 Patent, the relevant functionality is the data signaling protocol used by the WD PC SN530 NVMe SSD, which the complaint alleges operates in compliance with the Open NAND Flash Interface (ONFI) standard (Compl. ¶31).
- For the '539 Patent, the relevant functionality is the output buffer circuitry within the SanDisk memory chip. The complaint alleges these circuits contain the claimed driver and predriver architecture (Compl. ¶63).
- For the '233 Patent, the relevant functionality is the physical 3D architecture of the SanDisk memory chip, specifically the arrangement of vertical semiconductor pillars relative to a common contact plug (Compl. ¶98).
IV. Analysis of Infringement Allegations
'369 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A system comprising: a controller ... and a memory | The Western Digital PC SN530 NVMe SSD is a system [A] that includes a controller [B] and a memory [K]. | ¶32, ¶33, ¶37 | col. 3:9-11 |
| the controller being adapted to send out a first data strobe signal and a write data signal in a write operation, the write data signal being synchronized with the first data strobe signal | The controller is adapted to send out a first data strobe signal [C] and a write data signal [D], which is synchronized with the strobe signal [E], as shown in the ONFI standard data input timing diagram. A diagram depicts this synchronization (Compl. p. 10, Fig. 71). | ¶34 | col. 3:12-16 |
| the memory being adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation | The memory is adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation [L]. | ¶38 | col. 3:20-23 |
| the memory being adapted, in the read operation, to output the read data strobe signal in response to the second data strobe signal... | The memory is adapted in a read operation to output the read data strobe signal [M], which the complaint alleges is in response to the second data strobe signal. | ¶39 | col. 3:23-26 |
| ...and to send the read data signal synchronized with the read data strobe signal | The memory is adapted to send the read data signal synchronized with the read data strobe signal [M]. | ¶39 | col. 3:27-29 |
- Identified Points of Contention:
- Scope Questions: A primary question is whether the memory's generation of a read strobe signal (RDQS) under the ONFI standard occurs "in response to the second data strobe signal" from the controller, as the claim requires. A defendant may argue the RDQS is generated in response to a read command, not a distinct strobe signal, potentially creating a mismatch with the claim language.
- Technical Questions: What evidence demonstrates that the accused SSD, as sold and operated, actually performs according to the specific ONFI timing diagrams cited in the complaint?
RE43,539 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an output buffer circuit ... comprising a main driver | The accused SSD includes an output buffer circuit with a main driver [A]. The complaint supports this with a circuit diagram from a TechInsights report on a purportedly similar Toshiba chip (Compl. p. 21, Fig. 4.11). | ¶63 | col. 11:58-62 |
| said main driver including at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load | The main driver includes at least a pair of a first p-channel and first n-channel MOS transistor for driving a load [B]. A circuit diagram depicts this alleged pair of transistors (Compl. p. 23, Fig. 4.11.1.1). | ¶64 | col. 11:62-65 |
| a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor | The accused device includes a predriver [D] with outputs that allegedly drive only the first n-channel and first p-channel MOS transistors of the main driver [L]. | ¶66, ¶74 | col. 12:1-4 |
| said predriver comprising at least a pair of a second p-channel MOS transistor and a second n-channel MOS transistor for driving said load in coaction with said first...transistor | The predriver includes a pair of a second p-channel and second n-channel MOS transistor for driving the load in coaction with the first p-channel and first n-channel transistors [C]. | ¶65 | col. 11:65-67 |
| at least one fifth n-channel MOS transistor for driving said first p-channel MOS transistor in coaction with said third n-channel MOS transistor | The accused device includes at least one fifth n-channel MOS transistor [G] for driving the first p-channel MOS transistor in coaction with the third n-channel MOS transistor [E]. | ¶69 | col. 12:8-11 |
- Identified Points of Contention:
- Evidentiary Questions: The infringement allegations for the '539 Patent rely on a third-party teardown report of a Toshiba memory chip, which is alleged to be "substantially similar" to the accused SanDisk chip (Compl. ¶59, ¶62). A defendant will likely challenge the sufficiency of this indirect evidence to prove the internal circuitry of the accused product.
- Scope Questions: The claim requires a predriver with outputs for driving "only" the specified main driver transistors. The analysis will question whether the accused circuit, if proven to exist, meets this strict negative limitation or if its outputs have other connections.
V. Key Claim Terms for Construction
For U.S. Patent 7,697,369
- The Term: "in response to the second data strobe signal"
- Context and Importance: This term is critical for the read operation limitation. The infringement theory maps this to the memory's generation of a read data strobe (RDQS) signal. Practitioners may focus on whether the RDQS is truly generated "in response to" a strobe from the controller, or if it is more accurately described as being responsive to a general read command, which could place the accused operation outside the claim's scope.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent’s summary emphasizes that the invention provides a "new protocol" and that the data strobe is "completely separated from the clock signal," which may support an interpretation where any controller-sourced signal that prompts the RDQS (and isn't the clock) qualifies ('369 Patent, col. 1:25-26, 40-42).
- Evidence for a Narrower Interpretation: The detailed description and figures show the data strobe signal as a distinct signal line separate from the command/address signals ('369 Patent, FIG. 1, FIG. 2). A defendant could argue this implies the "second data strobe signal" must be a specific strobe pulse, not simply the arrival of a read command on the command bus.
For U.S. Reissue Patent RE43,539
- The Term: "a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor"
- Context and Importance: The term "only" imposes a significant negative limitation. The validity of the infringement allegation hinges on demonstrating that the accused predriver's outputs are exclusively connected as claimed. Practitioners may focus on this term because any additional electrical path from these specific predriver outputs to other components could serve to defeat a literal infringement allegation.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party might argue for a functional interpretation, where "driving only" refers to the primary, intended load, and incidental or minor secondary connections do not negate the element. The specification's focus is on the functional goal of adjusting slew rate and impedance ('539 Patent, col. 1:11-17).
- Evidence for a Narrower Interpretation: The claim language is unambiguous. Furthermore, the complaint itself highlights this limitation by alleging the connection is "directly connected only" (Compl. ¶74), suggesting Plaintiff anticipates a narrow construction. The patent's circuit diagrams, such as FIG. 3, depict clear, exclusive connections between the predriver and the main driver transistors, which supports a strict structural reading.
VI. Other Allegations
- Indirect Infringement: For all three patents-in-suit, the complaint alleges induced infringement under 35 U.S.C. §271(b). The allegations are based on Defendant having knowledge of the patents (at least since the September 6, 2022 notice letter) and acting with specific intent by providing products to customers and end-users, allegedly encouraging them to perform infringing acts "by the very nature of the products" (Compl. ¶¶40-44, 75-79, 104-108).
- Willful Infringement: The complaint alleges willful infringement for all three patents. The basis for this allegation is that Defendant "has known or should have known of this risk at least as early as September 6, 2022," the date of Plaintiff's notice letter (Compl. ¶¶49, 84, 113). This alleges willfulness based on post-notice conduct.
VII. Analyst’s Conclusion: Key Questions for the Case
Given that the asserted claims for the '369 and '539 patents have been cancelled or disclaimed via IPR, the focus of the litigation shifts almost entirely to the '233 patent. The central questions for the remainder of the case are likely to be:
A dispositive evidentiary question: Can Plaintiff meet its burden of proof for infringement of the '233 patent by relying on technical analysis of a "substantially similar" Toshiba chip to demonstrate the physical structure of the accused SanDisk/Western Digital component? The case may depend on whether the court finds this comparison sufficiently reliable to establish the facts of the accused device's construction.
A key question of claim construction and fact: Does the physical arrangement of the accused memory chip's vertical pillars meet the "uniformly arranged" limitation of the '233 patent, which requires the maximum pillar-to-contact plug distance to be no more than twice the minimum distance? This will involve both construing the claim term and applying it to the factual evidence of the chip's layout.