DCT
8:23-cv-00039
Longitude Licensing Ltd v. Amazon.com Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Limited (Ireland)
- Defendant: Amazon.com, Inc. (Delaware)
- Plaintiff’s Counsel: Russ, August & Kabat
- Case Identification: 8:23-cv-00039, C.D. Cal., 01/09/2023
- Venue Allegations: Plaintiff alleges venue is proper as Defendant is subject to personal jurisdiction and maintains regular and established places of business within the district, including in Los Angeles, Santa Monica, and Irvine.
- Core Dispute: Plaintiff alleges that Defendant’s products incorporating certain Western Digital semiconductor memory components infringe four patents related to memory system architecture, output buffer circuits, 3D semiconductor device structure, and on-chip voltage generation.
- Technical Context: The patents-in-suit concern fundamental technologies for the design and operation of high-speed, high-density semiconductor memory, a critical component in nearly all modern electronics from consumer devices to cloud computing infrastructure.
- Key Procedural History: The complaint states that Plaintiff has licensed the patents-in-suit to a majority of the memory industry but that Western Digital, a component supplier for the accused Amazon products, has refused to take a license. Prior to this suit, Plaintiff and Western Digital engaged in an arbitration over licensing obligations, which was dismissed on jurisdictional grounds. Plaintiff provided Defendant with notice of the alleged infringement by letter on September 6, 2022. Subsequent to the filing of this complaint, inter partes review (IPR) proceedings were initiated against the ’369 and ’539 patents, resulting in the cancellation or disclaimer of all asserted claims.
Case Timeline
| Date | Event |
|---|---|
| 2002-12-16 | U.S. Patent RE43,539 Priority Date |
| 2006-06-08 | U.S. Patent 7,697,369 Priority Date |
| 2010-04-13 | U.S. Patent 7,697,369 Issue Date |
| 2012-07-24 | U.S. Patent RE43,539 Issue Date |
| 2014-04-02 | ONFI Standard Revision 4.0 Date Mentioned in Complaint |
| 2014-09-09 | U.S. Patent 9,207,701 Priority Date |
| 2015-10-01 | U.S. Patent 9,379,233 Priority Date |
| 2015-12-08 | U.S. Patent 9,207,701 Issue Date |
| 2016-06-28 | U.S. Patent 9,379,233 Issue Date |
| 2022-09-06 | Plaintiff sends notice letter to Defendant |
| 2023-01-09 | Complaint Filing Date |
| 2023-07-14 | IPR filed challenging the ’369 Patent |
| 2023-08-08 | IPR filed challenging the ’539 Patent |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,697,369 - "System with Controller and Memory"
The Invention Explained
- Problem Addressed: The patent’s background section describes conventional memory systems where data transfer signals (data strobes) are synchronized with a master clock signal, which can introduce complexity and limitations (’369 Patent, col. 1:7-22).
- The Patented Solution: The invention proposes a data transfer protocol where the data strobe signal is independent of and completely separated from the system clock signal (’369 Patent, Abstract). In this system, a controller generates distinct data strobe signals for both write and read operations, and the memory generates a read data strobe signal in direct response to the controller’s read strobe, decoupling high-speed data transfer from the main system clock (’369 Patent, col. 1:28-42). This architecture is illustrated in the patent's Figure 1 (’369 Patent, Fig. 1).
- Technical Importance: This approach can simplify system design and allow for greater flexibility in interfacing with memory components that operate at different speeds than the main system clock (’369 Patent, col. 3:39-47).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶30).
- Claim 1 recites a system comprising:
- A controller adapted to send a first data strobe and a synchronized write data signal in a write operation.
- The controller is also adapted to send a second data strobe signal in a read operation and receive a read data signal synchronized with a read data strobe signal that is responsive to the second data strobe.
- A memory adapted to receive the write data signal synchronized with the first data strobe.
- The memory is also adapted to output the read data strobe signal in response to the second data strobe signal and send the read data signal synchronized with that read data strobe signal.
U.S. Patent No. RE43,539 - "Output Buffer Circuit and Integrated Semiconductor Circuit Device With Such Output Buffer Circuit"
The Invention Explained
- Problem Addressed: The invention addresses the challenge of designing high-speed output buffer circuits for semiconductor devices that can precisely control signal characteristics like output impedance and slew rate (the rate of voltage change) to ensure signal integrity (’539 Patent, col. 11:15-21).
- The Patented Solution: The patent discloses a multi-stage output buffer circuit featuring a "main driver" and a "predriver" (’539 Patent, Abstract). The main driver uses multiple sets of transistors to drive the output load. The key architectural feature is that the predriver’s outputs are connected to drive only the first p-channel and first n-channel transistors of the main driver, providing a distinct control pathway for the initial output stage (’539 Patent, col. 13:9-13). Other transistor pairs in the main driver act in "coaction" to shape the final output waveform (’539 Patent, Abstract).
- Technical Importance: This segmented driver architecture allows for fine-tuned control over signal rise and fall times, which is critical in high-frequency memory interfaces to prevent data corruption caused by signal reflections and other transmission line effects (’539 Patent, col. 11:15-21).
Key Claims at a Glance
- The complaint asserts at least independent claim 1 (Compl. ¶56).
- Claim 1, as corrected, recites an output buffer circuit comprising:
- A main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to data.
- A predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor.
U.S. Patent No. 9,379,233 - "Semiconductor Device"
- Technology Synopsis: This patent addresses challenges in 3D NAND memory architecture, where multiple vertical transistors are connected in parallel. To ensure consistent performance, the invention proposes a structure where the vertical semiconductor pillars are "uniformly arranged" around a shared metal contact plug, which connects to a shared lower diffusion layer, thereby stabilizing electrical characteristics across the transistor array (’233 Patent, Abstract; col. 2:6-11).
- Asserted Claims: At least independent claim 1 (Compl. ¶92).
- Accused Features: The complaint accuses the SanDisk memory chip within the Western Digital PC SN530 NVMe SSD of infringing, alleging its array of semiconductor pillars is "uniformly arranged near the lower diffusion side contact" as claimed (Compl. ¶99, ¶104).
U.S. Patent No. 9,207,701 - "Supply Voltage Generating Circuit"
- Technology Synopsis: The patent describes a supply voltage generating circuit (e.g., a charge pump) designed for efficiency across different external power supply voltages. The solution involves a circuit with multiple "booster stages" and a selection mechanism that changes the number of active stages based on the input voltage level, coupling a selected input node to the booster circuitry to produce a desired output voltage (’701 Patent, Abstract; col. 10:1-7).
- Asserted Claims: At least independent claim 1 (Compl. ¶121).
- Accused Features: The complaint accuses the SanDisk FKB7 NAND Flash memory within the Amazon Echo Show 10. It alleges the chip performs a method of selecting between different power supply voltages and changing the number of active booster stages in its voltage generation circuitry in response to that selection (Compl. ¶127-129).
III. The Accused Instrumentality
Product Identification
The complaint accuses multiple product categories sold by Amazon. For the ’369 and ’539 patents, the lead accused product is the Western Digital PC SN530 NVMe SSD, which contains a SanDisk memory chip (Compl. ¶29, ¶57). For the ’233 patent, the accused instrumentality is the SanDisk memory chip within that same SSD (Compl. ¶99). For the ’701 patent, the lead accused product is the Amazon Echo Show 10, which allegedly contains an infringing Western Digital FKB7 NAND flash memory chip (Compl. ¶120-121).
Functionality and Market Context
The accused SSDs are solid-state storage devices used in a wide range of computing products. The complaint alleges these SSDs operate in compliance with the Open NAND Flash Interface (ONFI) standard, a key industry specification for memory component communication (Compl. ¶31). The Amazon Echo Show 10 is a smart display device. The infringement allegations focus on the technical operation of the memory controller and memory chip components within these commercial products.
IV. Analysis of Infringement Allegations
’369 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a controller adapted to send out a first data strobe signal and a write data signal in a write operation, the write data signal being synchronized with the first data strobe signal... | The SSD controller sends a data strobe signal (DQS) and a write data signal (DQ) that are synchronized during a write operation, as shown in an ONFI standard timing diagram. | ¶34 | col. 7:16-21 |
| ...the controller being adapted, in a read operation, to send out a second data strobe signal and to receive a read data signal in synchronization with a read data strobe signal... | The SSD controller sends a second data strobe signal (RE_t/RE_c) and receives a read data signal (DQ) synchronized with a read data strobe signal (DQS), as shown in an ONFI standard timing diagram. | ¶35 | col. 7:21-27 |
| a memory adapted to receive the write data signal in synchronization with the first data strobe signal in the write operation... | The SSD’s NAND flash memory chip receives the write data signal synchronized with the first data strobe signal during a write operation. | ¶38 | col. 7:28-31 |
| ...the memory being adapted, in the read operation, to output the read data strobe signal in response to the second data strobe signal and to send the read data signal synchronized with the read data strobe signal. | The SSD’s NAND flash memory outputs the read data strobe signal in response to the controller’s second data strobe signal and sends the read data synchronized with it. | ¶39 | col. 7:31-36 |
- Visual Evidence: The complaint provides an annotated photograph of the accused SSD, identifying the overall device as the claimed "system" and a specific chip as the "controller" (Compl. p. 8). It also includes timing diagrams from the ONFI standard to illustrate the synchronized signaling for write and read operations (Compl. p. 9, 12).
- Identified Points of Contention:
- Scope Questions: A potential dispute may arise over whether an integrated SSD, with a controller and memory on a single printed circuit board, constitutes the claimed "system" comprising a "controller" and a "memory," which are depicted as distinct functional blocks in the patent (’369 Patent, Fig. 1).
- Technical Questions: The infringement theory relies on the accused product’s compliance with the ONFI standard. A factual question for the court may be whether the product's actual operation precisely mirrors the specific signaling relationships required by the claim, such as the memory outputting its read strobe "in response to" the controller's second strobe signal.
’539 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a main driver having at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to said data... | The accused memory chip includes a main driver circuit with a pair of p-channel and n-channel transistors for driving an output load, as depicted in a third-party technical analysis report. | ¶63-64 | col. 12:60-63 |
| ...a predriver with outputs for driving only said first n-channel MOS transistor and only said first p-channel MOS transistor. | The accused chip allegedly contains a predriver circuit whose outputs are directly connected only to the gates of the first p-channel and first n-channel transistors of the main driver. | ¶66, ¶74 | col. 13:9-13 |
- Visual Evidence: The complaint's infringement theory is supported by annotated circuit diagrams from a TechInsights teardown report, which identify the alleged "main driver" (Compl. p. 19) and "predriver" (Compl. p. 23). Another diagram is used to allege that the predriver's output is connected "only to" the first transistors of the main driver (Compl. p. 32).
- Identified Points of Contention:
- Scope Questions: The construction of "driving only" will be central. A dispute may arise over whether this term requires absolute electrical isolation from all other components, or if it permits other incidental electrical influences that do not constitute "driving."
- Technical Questions: The infringement case for this patent rests on the allegation that the accused SanDisk memory chip is "substantially the same" as a Toshiba chip analyzed in a third-party report (Compl. ¶62). A key factual question will be whether this equivalence holds and if the circuit diagrams from the report accurately represent the accused product's operation as it relates to the claim limitations.
V. Key Claim Terms for Construction
’369 Patent: "in response to the second data strobe signal"
- The Term: "in response to the second data strobe signal"
- Context and Importance: This phrase in claim 1 defines the required causal relationship between the controller's read command and the memory's generation of the read data strobe signal. The validity of the infringement allegation depends on proving that the controller's signal directly causes the memory to output its strobe, rather than the memory generating it based on other internal timing. Practitioners may focus on this term because it establishes the specific handshaking protocol required by the claim.
- Intrinsic Evidence for a Broader Interpretation: The specification states the memory "generates the RDQS signal from the data strobe signal in the read operation," which may support an interpretation where the controller's signal is the primary trigger (’369 Patent, col. 4:62-64).
- Intrinsic Evidence for a Narrower Interpretation: The patent describes this function occurring within a specific "data I/O synchronous signal generating section," which may suggest a more complex internal process where the controller's signal is merely one of several inputs, not the sole trigger (’369 Patent, col. 4:61-64).
’539 Patent: "driving only"
- The Term: "driving only said first n-channel MOS transistor and only said first p-channel MOS transistor"
- Context and Importance: This limitation in claim 1 defines the architectural separation that is a core aspect of the invention. The infringement analysis will turn on whether the accused predriver's outputs are exclusively connected to the specified main driver transistors. Practitioners may focus on this term because its interpretation—whether it means absolute electrical isolation or merely functional purpose—will be dispositive.
- Intrinsic Evidence for a Broader Interpretation: A party could argue the term should be interpreted functionally, meaning the predriver's primary and intended purpose is to drive the first set of transistors, even if incidental electrical coupling to other circuit elements exists.
- Intrinsic Evidence for a Narrower Interpretation: The abstract and detailed descriptions repeatedly tie specific predriver components to driving specific main driver components (’539 Patent, Abstract). This may support a narrow construction requiring a direct, physically exclusive connection, where any other connection would defeat the "only" limitation.
VI. Other Allegations
- Indirect Infringement: For all four patents, the complaint alleges induced infringement, asserting that Defendant encourages its customers to infringe by the inherent nature and operation of the accused products (Compl. ¶42, ¶77, ¶107, ¶132).
- Willful Infringement: For all four patents, the complaint alleges willful infringement based on Defendant’s knowledge of the patents and the alleged infringement since at least the date of Plaintiff's notice letter on September 6, 2022 (Compl. ¶49, ¶84, ¶114, ¶139).
VII. Analyst’s Conclusion: Key Questions for the Case
This case presents several distinct technical and legal questions for the court's determination.
- A primary issue for the ’369 patent is one of definitional scope: does an integrated Solid State Drive (SSD), where a controller and memory chips are co-located on a single board, meet the claim limitation of a "system" comprising a distinct "controller" and "memory," as envisioned by the patent?
- For the ’539 and ’701 patents, a key evidentiary question will be one of technical equivalence: can Plaintiff demonstrate that the accused SanDisk chips are functionally and structurally equivalent to the different Toshiba chips analyzed in the third-party reports upon which the infringement allegations are based?
- A central dispute for the ’233 patent will likely be a structural question: do the semiconductor pillars in the accused 3D NAND chip meet the "uniformly arranged" limitation in a manner that achieves the patent's stated technical objective, or is the physical layout functionally distinct from what the claim requires?
Finally, while outside the four corners of the complaint, the subsequent cancellation or disclaimer of the asserted claims of the ’369 and ’539 patents in inter partes review proceedings raises fundamental questions about the continued viability of Counts I and II of this litigation.