DCT
8:23-cv-02054
VisionX Tech LLC v. OmniVision Tech Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: VisionX Technologies, LLC (Texas)
- Defendant: OmniVision Technologies Inc. (Delaware)
- Plaintiff’s Counsel: One LLP
- Case Identification: 8:23-cv-02054, C.D. Cal., 11/01/2023
- Venue Allegations: Venue is alleged to be proper based on Defendant maintaining offices within the Central District of California where a substantial portion of the alleged infringing activities occurred.
- Core Dispute: Plaintiff alleges that Defendant’s stacked CMOS image sensor products infringe three patents related to the structure and manufacturing methods of semiconductor image sensors.
- Technical Context: The technology at issue involves stacked, backside-illuminated (BSI) CMOS image sensors, a critical technology for enabling high-performance, compact cameras in ubiquitous devices like smartphones and automotive systems.
- Key Procedural History: The asserted patents were originally assigned to Dongbu HiTek Co., Ltd., a South Korean semiconductor foundry. Plaintiff VisionX Technologies, LLC asserts it is now the sole and exclusive owner of all rights in the patents.
Case Timeline
| Date | Event |
|---|---|
| 2007-03-14 | ’366 Patent Priority Date |
| 2007-12-28 | ’808 Patent Priority Date |
| 2008-11-05 | ’143 Patent Priority Date |
| 2011-01-11 | ’808 Patent Issue Date |
| 2011-01-11 | ’366 Patent Issue Date |
| 2011-10-11 | ’143 Patent Issue Date |
| 2023-11-01 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,867,808
- Patent Identification: U.S. Patent No. 7,867,808, "Image Sensor and Method for Manufacturing the Same," issued January 11, 2011.
- The Invention Explained:
- Problem Addressed: The patent’s background section describes challenges with conventional CMOS image sensors (CIS) where the light-sensitive photodiode and the processing transistor are arranged horizontally on a substrate. This arrangement can reduce the sensor's light-gathering area (fill factor) and complicates the optimization of manufacturing processes for the different components. (’808 Patent, col. 1:11-44).
- The Patented Solution: The invention discloses a method for vertically integrating an image sensor. A first substrate containing circuitry is bonded to a second substrate that has a photodiode formed in a crystalline semiconductor layer. A key step involves removing a lower portion of the second substrate to expose the photodiode to light from the backside, which improves sensitivity. The patent also describes using specific ion implantation layers to electrically isolate adjacent pixels and reduce electrical noise. (’808 Patent, Abstract; col. 2:1-12, 44-51).
- Technical Importance: This stacked, backside-illuminated (BSI) architecture allows for smaller pixels with improved performance, a critical innovation for developing the high-resolution, compact cameras used in modern electronics. (Compl. ¶7).
- Key Claims at a Glance:
- The complaint asserts independent claim 1. (Compl. ¶17, 22).
- The essential elements of method claim 1 include:
- providing a first substrate and forming circuitry with a metal interconnection over it;
- forming a photodiode in a crystalline semiconductor layer of a second substrate;
- forming an ion implantation isolation layer within the photodiode, which itself comprises forming multiple, specifically defined conduction and isolation layers;
- bonding the first and second substrates to connect the photodiode to the metal interconnection; and
- removing a lower portion of the second substrate to expose the photodiode.
- The complaint alleges infringement of "one or more claims," preserving the right to assert additional claims. (Compl. ¶17).
U.S. Patent No. 8,035,143
- Patent Identification: U.S. Patent No. 8,035,143, "Semiconductor Device and Method for Manufacturing the Same," issued October 11, 2011.
- The Invention Explained:
- Problem Addressed: The patent identifies light loss and design constraints as problems in conventional image sensors. When light has to travel through the metal interconnection layers on the front of a chip to reach the photodiode, sensitivity is degraded. This also restricts the design of the interconnection routing. (’143 Patent, col. 1:20-31).
- The Patented Solution: The patent describes a backside-illuminated image sensor structure. The invention centers on a "connection via metal" that passes from the front surface to the back surface of the semiconductor substrate. This via is formed with a "projection part" that extends beyond the back surface. An insulating layer is then formed on the back surface around this projection, and a metal pad is placed on the insulating layer to cover and make contact with the projection, creating a robust electrical connection to the backside. (’143 Patent, Abstract; col. 2:4-14).
- Technical Importance: This structure provides a specific, reliable method for creating through-substrate electrical contacts in BSI sensors, facilitating the design of more sensitive and complex imaging devices. (Compl. ¶7-8).
- Key Claims at a Glance:
- The complaint asserts independent claim 1. (Compl. ¶40, 44).
- The essential elements of apparatus claim 1 include:
- a semiconductor substrate with a readout circuitry and a photodiode area on a first surface;
- a metal interconnection layer on the first surface;
- a connection via metal extending from the first to a second surface, with a "projection part" extending from the second surface;
- an insulating layer on the second surface that exposes the projection part while surrounding a portion of its lateral side; and
- a metal pad on the insulating layer that covers the projection part, where the insulating layer is thinner than the height of the projection part.
- The complaint alleges infringement of "one or more claims," preserving the right to assert additional claims. (Compl. ¶40).
Multi-Patent Capsule: U.S. Patent No. 7,868,366
- Patent Identification: U.S. Patent No. 7,868,366, "Image Sensor and Method for Fabricating the Same," issued January 11, 2011.
- Technology Synopsis: This patent discloses an image sensor with a stacked architecture designed to enhance optical characteristics. It describes a first semiconductor substrate (containing unit pixels) disposed on a second semiconductor substrate (containing support circuitry). The invention details the structure of vias that electrically connect the two substrates and the specific arrangement of metal interconnections and dielectric layers. (’366 Patent, Abstract; col. 2:33-51).
- Asserted Claims: The complaint asserts independent claim 1. (Compl. ¶59, 63).
- Accused Features: The complaint accuses the physical structure of OmniVision's "stacked" products, such as the OV23850. The infringement theory focuses on the layered composition, including the two semiconductor substrates, the vias connecting them, and the various metal and dielectric layers that allegedly correspond to the elements of the asserted claim. (Compl. ¶62-66).
III. The Accused Instrumentality
Product Identification
- The complaint accuses numerous OmniVision image sensor chips, including those in the "PureCel-S," "PureCel Plus-S," and "stacked" product families, such as the OV60A, OV50A, and OV23850. (Compl. ¶18, 41, 60).
Functionality and Market Context
- The accused products are stacked CMOS image sensors (CIS). The complaint alleges they are manufactured by bonding a CIS wafer, which contains the photodiodes, to an image signal processor (ISP) wafer, which contains the processing logic. (Compl. ¶23, 45, 64). The complaint presents scanning electron microscope (SEM) cross-sections of the accused products to illustrate their internal structure, including the stacked dies, interconnects, and pixel-level doping layers. (Compl. ¶23, Figure 1). Figure 1 from the complaint is an SEM cross-section showing the stacked CIS and ISP dies of an accused OV60A sensor. (Compl. ¶23).
- The complaint alleges these sensors are key components in a wide array of commercially significant products, including smartphones, automotive cameras, VR/AR headsets, and medical imaging devices, and are sold to major electronics manufacturers. (Compl. ¶8, 20, 31, 45).
IV. Analysis of Infringement Allegations
’808 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| providing a first substrate; | The accused OV60A sensor provides an Image Signal Processor (ISP) substrate. | ¶27, p. 11 | col. 2:25-28 |
| forming circuitry including a metal interconnection over the first substrate; | Circuitry, including metal interconnections such as ISP M1-M6 Cu, is formed over the ISP substrate. | ¶27, p. 12 | col. 2:25-28 |
| forming a photodiode in a crystalline semiconductor layer of a second substrate; | A photodiode is formed in the crystalline semiconductor layer of a second CMOS Image Sensor (CIS) substrate. An SEM image shows the location of the alleged photodiode. (Compl. ¶27, p. 13). | ¶27, p. 13 | col. 2:29-32 |
| forming an ion implantation isolation layer in the photodiode; | An isolation layer of P-type impurity ions is allegedly formed in the photodiode structure. | ¶27, p. 14 | col. 2:32-34 |
| bonding the first substrate to the second substrate to connect the photodiode to the metal interconnection; | The ISP and CIS substrates are connected via direct bonding interconnects (DBIs), which connect the photodiode on the CIS substrate to the metal interconnection on the ISP substrate. (Compl. ¶26). | ¶27, p. 15 | col. 4:22-34 |
| and removing a lower portion of the second substrate to expose the photodiode, | A lower portion of the CIS substrate is removed to expose the photodiode for backside illumination. | ¶27, p. 16 | col. 4:40-45 |
| wherein forming the photodiode comprises: forming a second conduction type conduction layer in the crystalline semiconductor layer; | A P-type conduction layer is allegedly formed in the crystalline semiconductor layer of the CIS substrate. | ¶27, p. 17 | col. 2:35-39 |
| and forming a first conduction type conduction layer over the second conduction type conduction layer, | An N-type conduction layer is allegedly formed over the P-type conduction layer. | ¶27, p. 17 | col. 2:35-39 |
| wherein forming the ion implantation isolation layer...comprises forming a second conduction type first ion implantation isolation layer... | Forming the isolation layer allegedly includes forming P-type impurity ions as a first isolation layer over the N-type conduction layer. An annotated image highlights these alleged layers. (Compl. ¶27, p. 18). | ¶27, p. 18 | col. 2:48-51 |
| wherein forming the ion implantation isolation layer...comprises forming a second conduction type second ion implantation isolation layer... | Forming the isolation layer allegedly includes forming P-type impurity ions as a second isolation layer at the interface between pixels. A color-coded image depicts the alleged doping regions. (Compl. ¶25, Figure 3). | ¶27, p. 19 | col. 2:45-48 |
’143 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor substrate formed on a first surface thereof with a readout circuitry and a photodiode area; | The accused OV50A sensor includes a pixel array with photodiodes and readout circuitry situated on a first surface of a CIS substrate. | ¶46, p. 25 | col. 9:4-7 |
| a metal interconnection layer formed on the first surface; | A metal interconnection layer (e.g., CIS M1-M3 Cu) is situated on the first surface of the CIS substrate. | ¶46, p. 26 | col. 9:7-8 |
| a connection via metal extending from the first surface to a second surface..., the connection via metal having a projection part...; | A copper connection via metal is alleged to extend from the first surface to the second surface of the CIS substrate. The complaint identifies a "projection part (125a)" that projects from the second surface. (Compl. ¶46, p. 27). | ¶46, p. 27 | col. 9:9-13 |
| an insulating layer formed on the second surface...to expose the projection part while surrounding a portion of a lateral side...; | An insulating layer is allegedly formed on the second surface of the CIS substrate, leaving the projection part exposed while surrounding part of its side. An SEM image with a purple overlay illustrates this feature. (Compl. ¶46, p. 28). | ¶46, p. 28 | col. 9:14-18 |
| a metal pad formed on the insulating layer such that the metal pad covers the projection part, | A metal pad (ISP M7) is allegedly formed on the insulating layer and covers the projection part. | ¶46, p. 29 | col. 9:19-22 |
| wherein the insulating layer has a thickness thinner than a projection height of the projection part. | The complaint alleges that the thickness of the insulating layer is less than the height of the projection part, providing a diagram to illustrate the alleged dimensions. (Compl. ¶46, p. 30). | ¶46, p. 30 | col. 9:23-25 |
- Identified Points of Contention:
- Scope Questions: For the ’808 patent, a central question will be whether the accused product's various P-type and N-type doped regions constitute the specifically claimed sequence of "conduction type" and "ion implantation isolation" layers. The claim's detailed "wherein" clauses create multiple potential points of mismatch.
- Technical Questions: For the ’143 patent, the dispute may focus on a question of physical structure and dimension: does the accused product's through-substrate via have a feature that meets the definition of a "projection part," and can objective measurement confirm that the surrounding "insulating layer" is "thinner than a projection height" of that part as required by the claim?
V. Key Claim Terms for Construction
U.S. Patent No. 7,867,808
- The Term: "ion implantation isolation layer"
- Context and Importance: This term is recited multiple times in claim 1, each with a different specific modifier (e.g., "second conduction type first ion implantation..."). The infringement analysis depends entirely on mapping the accused product’s complex doping structure onto these limitations. Practitioners may focus on this term because its construction will determine whether the various P-type layers in the accused product, created for different purposes like pixel isolation and passivation, fall within the claim's scope.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification suggests the layer's primary purpose is functional, stating it achieves "pixel-to-pixel isolation" and can be used "instead of using a related art shallow trench isolation (STI) process." (’808 Patent, col. 2:55-62). This could support an interpretation covering any implanted layer that provides isolation.
- Evidence for a Narrower Interpretation: The claim language itself is highly specific, defining a sequence of first and second isolation layers of a particular conduction type relative to other layers. The specification describes forming these layers via specific "blanket-ion implantation" steps, which could be used to argue for a narrower, process-limited definition. (’808 Patent, col. 3:34-51).
U.S. Patent No. 8,035,143
- The Term: "projection part projecting from the second surface"
- Context and Importance: This geometric feature is the lynchpin of claim 1. The infringement case hinges on identifying this specific structure in the accused devices. The construction of "projection part" will be critical, as it dictates the reference point for the key limitation that the surrounding insulating layer must be thinner than the projection's height.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes this feature as being formed when a back grinding process exposes the "end of the connection via metal 125," which then "forms a projection part 125a." (’143 Patent, col. 10:55-61). This could support a reading on any portion of the via that extends beyond the ground surface.
- Evidence for a Narrower Interpretation: The figures, such as Figure 4, depict a distinct, pillar-like structure that protrudes significantly. A defendant could argue that "projection part" implies a specific shape or aspect ratio that is intentionally formed, rather than any incidental unevenness resulting from a manufacturing process. (’143 Patent, Fig. 4).
VI. Other Allegations
- Indirect Infringement: For all three patents, the complaint alleges induced infringement. The factual basis is Defendant's alleged role in encouraging and facilitating its customers' (e.g., Microsoft, Dell, Tesla) infringement by providing the accused sensors along with "specifications and promotional literature," "user manuals," and "technical assistances" that instruct on how to incorporate the sensors into infringing end products like smartphones and vehicles. (Compl. ¶29-30, 34-35; ¶49, 53-54; ¶69, 73-74).
- Willful Infringement: The complaint alleges willful infringement for all three patents. The allegation is based on Defendant having "actual knowledge" of the patents and their infringement "at least as of November 1, 2023" (the filing date of the complaint) and, in the alternative, knowledge as of the date of the complaint itself. (Compl. ¶31-33, ¶50-52, ¶70-72).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of structural correspondence: Do the complex, multi-layered physical architectures of OmniVision's stacked image sensors, as revealed through technical analysis, satisfy every specific structural and dimensional limitation recited in the asserted claims, or are there material differences in the arrangement and properties of the substrates, vias, and doped layers?
- A key legal question will be one of definitional precision: The case will likely depend on the court's construction of highly technical claim terms. For example, can the '808 patent's "ion implantation isolation layer" be construed broadly to cover any doped region providing electrical isolation, or is it limited to the specific sequence and type described in the patent's embodiment? Similarly, does the '143 patent's "projection part" require a distinct, intentionally-formed structure, or can it read on any portion of a via extending beyond a substrate's surface?