DCT

8:24-cv-01903

BiTMICRO LLC v. Western Digital Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 8:24-cv-01903, C.D. Cal., 09/03/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Western Digital has a physical presence in the Central District of California, conducts business in the district, and has committed alleged acts of patent infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s solid-state drives (SSDs) and enterprise storage platforms infringe four patents related to multi-profile memory controllers, mapping tables for optimizing memory operations, networked memory systems, and direct memory access with encryption.
  • Technical Context: The technologies at issue concern methods for improving the performance, data integrity, reliability, and security of flash-based solid-state storage, a foundational technology in modern computing.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of the asserted patents based on several events. Notably, it alleges that the '190 Patent was repeatedly cited by the U.S. Patent and Trademark Office against a patent application filed by SanDisk (later acquired by Western Digital) beginning in 2016. The complaint also alleges that Plaintiff’s predecessor approached Western Digital regarding its patents around 2016 and that Western Digital was served a subpoena related to the '190 Patent in a 2018 International Trade Commission proceeding. These allegations form the basis for the claim of willful infringement.

Case Timeline

Date Event
2006-03-17 ’389 Patent Earliest Priority Date
2006-06-08 ’740 Patent Earliest Priority Date
2009-09-04 ’190 Patent Earliest Priority Date
2010-05-11 ’389 Patent Issue Date
2011-08-30 ’740 Patent Issue Date
2013-03-15 ’205 Patent Earliest Priority Date
2015-09-15 ’190 Patent Issue Date
2016-01-01 Plaintiff's predecessor allegedly approached Defendant regarding patents (approximate)
2016-04-06 ’190 Patent first cited by USPTO against a SanDisk patent application
2016-05-12 Western Digital completes acquisition of SanDisk
2018-01-23 ’205 Patent Issue Date
2018-05-18 BiTMICRO served subpoena on Western Digital in ITC action involving ’190 Patent
2024-09-03 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,135,190 - Multi-profile memory controller for computing devices (issued Sep. 15, 2015)

The Invention Explained

  • Problem Addressed: The patent's background describes a limitation in prior memory controllers, which were typically designed to interact with memory devices that all shared a uniform set of characteristics, such as block size. This uniformity prevented controllers from varying read/write operations to optimize for different types of memory or data within a single system (Compl. ¶16; ’190 Patent, col. 1:20-29).
  • The Patented Solution: The invention is a "multi-profile memory controller" capable of operating with memory locations that are associated with different sets of attributes, or "device profiles." These profiles can define characteristics like memory device type, data size, and memory protocol (Compl. ¶¶16-17; ’190 Patent, col. 2:63-3:13). The controller analyzes an incoming memory request and selects an appropriate memory location based on a comparison of the request's requirements and the attributes stored in the various device profiles. This allows a single non-volatile storage device to be partitioned, for example, to use one portion as a high-performance cache and another for standard storage (Compl. ¶15; ’190 Patent, col. 3:14-25).
  • Technical Importance: This approach allows a storage device to gain the performance benefits of caching without requiring a separate physical cache device, while also preserving data in the cache partition during a power loss because it resides in non-volatile memory (Compl. ¶¶15-16).

Key Claims at a Glance

  • The complaint asserts independent claim 59 (Compl. ¶55).
  • Essential elements of claim 59 include:
    • An interface controller coupled to a memory device interface and an I/O device interface.
    • A memory store directly coupled to the memory device interface.
    • The controller performs a memory transaction by addressing a first memory location.
    • A first memory location and a second memory location are associated with a first and second device profile, respectively, and a difference exists between the profiles.
    • The first device profile is "optimal" for the data type of the transaction (e.g., random or sequential).
    • The controller identifies command details, obtains attributes from the first device profile, and uses those attributes for addressing.
    • The addressing includes selecting a transfer size that is a function of the transaction's data size and the first set of attributes.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,010,740 - Optimizing memory operations in an electronic storage device (issued Aug. 30, 2011)

The Invention Explained

  • Problem Addressed: The patent describes inefficiencies inherent in solid-state storage devices, such as write cycle limitations and the complexity of block-level addressing, which can increase write latency. Prior art solutions to these problems, such as adding more powerful processors or complex management algorithms, increased cost and design complexity (Compl. ¶¶21-22; ’740 Patent, col. 1:42-2:10).
  • The Patented Solution: The patent discloses an improved mapping table designed to optimize memory operations. The table structure efficiently associates sets of logical block addresses (LBAs), used by the host system, with corresponding sets of physical block addresses (PBAs) and associated "access parameters" on the physical memory chips (’740 Patent, col. 2:27-49). This mapping is structured to "increas[e] the likelihood" that the operational load will be optimally distributed across the device's resources, for instance by enabling interleaved or parallel memory operations to reduce latency and improve efficiency (Compl. ¶23; ’740 Patent, col. 2:14-21).
  • Technical Importance: The invention aims to enhance the performance and efficiency of SSDs by optimizing data placement and access through a structured mapping table, thereby minimizing the need for more costly hardware or complex management algorithms (Compl. ¶23).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶82).
  • Essential elements of claim 1 include:
    • A mapping table for optimizing memory operations.
    • A set of "logical fields" representing a plurality of LBA sets, where each set represents consecutive LBAs.
    • A set of "PBA fields" representing a set of PBAs, access parameters for the PBAs, and an association between the LBA sets and PBA sets.
    • The mapping table causes the device to perform "optimized memory operations" on memory locations associated with the PBAs when an I/O request is associated with the corresponding LBA sets.
  • The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsule: U.S. Patent No. 9,875,205

  • Patent Identification: U.S. Patent No. 9,875,205, "Network of memory systems," issued January 23, 2018.
  • Technology Synopsis: The patent addresses data distribution bottlenecks and reliability limitations in prior multi-chip memory systems, which lacked robust interconnect strategies (Compl. ¶28; ’205 Patent, col. 1:44-49). The disclosed solution is a large-scale memory system architecture comprising multiple flash memory modules and system controllers interconnected via a point-to-point communication bus topology, a design intended to enhance redundancy, throughput, and data access flexibility (Compl. ¶29; ’205 Patent, Abstract).
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶95).
  • Accused Features: The complaint accuses Western Digital's OpenFlex Data24 Series NVMe-oF storage platforms, which are alleged to be an apparatus comprising a communication bus interface, flash memory modules coupled to that interface, and a system controller that performs memory transactions via the interface to the modules (Compl. ¶¶40, 96-100). The complaint includes a photograph of the accused OpenFlex platform (Compl. ¶96, p. 33).

Multi-Patent Capsule: U.S. Patent No. 7,716,389

  • Patent Identification: U.S. Patent No. 7,716,389, "Direct memory access controller with encryption and decryption for non-blocking high bandwidth I/O transactions," issued May 11, 2010.
  • Technology Synopsis: The patent addresses the performance overhead associated with data encryption and decryption, which traditionally required computationally intensive processing and multiple inefficient memory-to-memory data transfers (Compl. ¶34; ’389 Patent, col. 2:4-10). The invention is a direct memory access (DMA) controller that integrates a "data processing core" for performing encryption and decryption, which allows the controller to intercept data and process it securely during a DMA transfer, eliminating the need for extra memory transfers and minimizing performance impact (Compl. ¶35; ’389 Patent, col. 2:27-35).
  • Asserted Claims: Independent claim 19 is asserted (Compl. ¶107).
  • Accused Features: The complaint accuses Western Digital SSDs featuring hardware encryption or self-encrypting drives, such as the Ultrastar DC SN861 (Compl. ¶¶41, 108). These products are alleged to contain a DMA controller that includes a "means for performing a DMA data transfer" (a DMA engine) coupled to a "means for performing data processing" (a cryptographic module) that encrypts or decrypts data (Compl. ¶¶112-113).

III. The Accused Instrumentality

Product Identification

  • The complaint names dozens of Western Digital and SanDisk-branded products, broadly categorized as:
    • SSDs with SLC caching capabilities (accused of infringing the ’190 Patent) (Compl. ¶38).
    • Non-Volatile Memory Express (NVMe) SSDs (accused of infringing the ’740 Patent) (Compl. ¶39).
    • OpenFlex Data24 Series NVMe-oF (over Fabrics) storage platforms (accused of infringing the ’205 Patent) (Compl. ¶40).
    • SSDs with hardware encryption or self-encrypting drives (accused of infringing the ’389 Patent) (Compl. ¶41).

Functionality and Market Context

  • The complaint focuses on specific technologies within the accused products. For the '190 patent, it highlights "SLC caching" (termed "nCache 3.0" in product literature), where a portion of Triple-Level Cell (TLC) NAND memory is configured to operate in a faster, more durable Single-Level Cell (SLC) mode to serve as a write cache (Compl. ¶¶61, 67). A specifications table from a product brief for the accused IX SN530 SSD illustrates the availability of both SLC and TLC configurations (Compl. ¶57, p. 19).
  • For the '740 patent, the allegations center on the use of a mapping table stored in DRAM to translate logical addresses (LBAs) from a host system to physical addresses (PBAs) on the NAND flash memory (Compl. ¶83). The complaint alleges these products use techniques like interleaving to optimize performance by distributing data across memory channels and planes (Compl. ¶84).
  • The accused products are positioned as high-performance storage solutions for a wide range of consumer, industrial, and enterprise data center applications (Compl. ¶¶1, 37).

IV. Analysis of Infringement Allegations

U.S. Patent No. 9,135,190 Infringement Allegations

Claim Element (from Independent Claim 59) Alleged Infringing Functionality Complaint Citation Patent Citation
an interface controller coupled to a memory device interface and an input/output (IO) device interface The Western Digital NVMe 1.4 compliant controller chip serves as the interface controller, connected to a memory bus (memory device interface) and a PCIe interface (I/O interface). ¶57-58 col. 3:26-30
a memory store The 96-layer 3D TLC NAND memory on the SSD constitutes the memory store. ¶59 col. 4:1-4
said interface controller disposed to perform a memory transaction by addressing a first memory location in the memory store The controller performs a write transaction by addressing a location within the portion of the TLC NAND memory reserved to act as an SLC cache. ¶61 col. 4:26-30
said first memory location and a second memory location respectively associated with a first device profile and a second device profile The first location is a cell in the SLC cache partition; the second is a cell in the non-cache TLC partition. Each is associated with a different profile. ¶62 col. 4:45-51
wherein said first device profile is optimal for a data type...comprises one of a random data type or a sequential data type The SLC cache profile is alleged to be optimal for write-intensive applications (both sequential and random) due to higher sustained write performance and endurance. ¶63 col. 4:52-57
said device profile representing a first set of attributes...and said second device profile representing a second set of attributes..., and a difference exists between said first and second device profiles The SLC cache profile has attributes associated with a write protocol of one bit per cell, which differs from the non-cache portion's write protocol of three bits per cell. ¶65 col. 4:58-64
said addressing of said first memory location includes selecting a transfer size for the memory transaction, wherein the transfer size is a function of a data size of the memory transaction and the first set of attributes The controller selects a transfer size for writing to the SLC cache based on the size of the data to be written, the remaining capacity of the cache, and the attributes of the SLC cache profile. ¶67 col. 5:10-15
  • Identified Points of Contention:
    • Scope Question: A central question may be whether different operational modes of the same physical memory cells (i.e., TLC NAND cells operating in a faster SLC mode) constitute distinct "device profiles" associated with different "memory locations" as contemplated by the patent. The dispute may focus on whether the patent requires physically distinct memory types or if a firmware-defined operational difference is sufficient.
    • Technical Question: The analysis may turn on whether the accused controller's process for managing its SLC cache—selecting where to write data and what size transfer to use—performs the specific functions of "obtaining the first set of attributes" and "using said attributes" in the manner required by the claim language.

U.S. Patent No. 8,010,740 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A mapping table for optimizing memory operations...in response to receiving an I/O transaction request initiated by a host The accused SSDs include a mapping table (e.g., in DRAM) to map logical block addresses (LBAs) to physical block addresses (PBAs). ¶83 col. 9:64-67
a set of logical fields...disposed for representing a plurality of LBA sets,...said first and second LBA sets each representing a set of consecutive LBAs The mapping table is alleged to include logical fields that represent sets of consecutive LBAs from the host. ¶85 col. 10:1-5
a set of PBA fields...disposed for representing a set of PBAs,...said PBAs each associated with a physical memory location in a memory store, said set of logical fields and said set of PBA fields disposed to associate said first and second LBA sets with said first and second PBAs The table includes fields representing PBAs that can be associated with different memory channels, lanes, buses, etc., and these fields associate the LBA sets with the PBA sets. ¶86 col. 10:6-14
and wherein, in response to receiving the I/O transaction request, said mapping table causes the electronic storage device to perform optimized memory operations... The controller allegedly uses the LBA-PBA mapping information to perform interleaving, which distributes read/write operations across memory locations to increase speed and efficiency. A diagram in the complaint illustrates the connection between a CPU, PCIe interface, and SSDs (Compl. ¶84, p. 28). ¶88 col. 10:15-24
  • Identified Points of Contention:
    • Scope Question: The dispute may center on whether the term "access parameters" as used in the patent reads on the specific information stored in the accused mapping tables. The construction of this term will be critical to determine if the accused tables have the claimed structure.
    • Technical Question: An evidentiary question will be whether the accused mapping table itself "causes" the optimized memory operations (like interleaving) in the manner required by the claim, or if that optimization is performed by separate controller logic that is not part of the claimed mapping table structure.

V. Key Claim Terms for Construction

For the ’190 Patent

  • The Term: "device profile"
  • Context and Importance: This term is the central inventive concept. The outcome of the infringement analysis for claim 59 hinges on whether Western Digital’s SLC caching technology—which configures a portion of its standard TLC memory to operate in a different, faster SLC mode—creates a distinct "device profile." Practitioners may focus on this term because if it is construed to require physically different memory technologies, the infringement case may be weakened, whereas a broader construction covering different operational modes of the same physical media may support the plaintiff's theory.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification provides a non-exhaustive list of attributes that can form a profile, including "the memory protocol or specification supported by the memory device" (’190 Patent, col. 3:9-11). Plaintiff may argue that the different write protocols for SLC mode (1 bit per cell) and TLC mode (3 bits per cell) constitute different "memory protocols," thus creating distinct profiles.
    • Evidence for a Narrower Interpretation: The patent's figures and description often refer to physically separate "Memory Device 10" and "Memory Device 12" when illustrating the concept (’190 Patent, Fig. 1; col. 4:4-7). Defendant may argue this context suggests a "device profile" is inherently tied to a physically distinct memory device, not just a logical partition or operational mode of a single device.

For the ’740 Patent

  • The Term: "access parameters"
  • Context and Importance: The claim requires the mapping table to include "PBA fields" that represent a set of PBAs and "access parameters for the PBAs." The definition of "access parameters" will determine what specific information must be present in the accused mapping table for it to meet this limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim states the "PBA disposed for representing a first set of access parameters," which could be interpreted to mean the PBA itself implicitly represents the parameters, or that the parameters are any data associated with the PBA used for optimization. The patent's objective is to "optimally distribute[]" the load, suggesting any parameter facilitating that goal could be covered (’740 Patent, col. 2:18-19).
    • Evidence for a Narrower Interpretation: The detailed description provides specific examples of access parameters, including a "bus identifier field," a "FDE [flash device engine] identifier field," and a "group identifier field" (’740 Patent, col. 6:34-38). Defendant may argue that "access parameters" should be limited to these or similar hardware-path-specific identifiers, and that general metadata would not suffice.

VI. Other Allegations

Willful Infringement

  • The complaint alleges that Western Digital’s infringement has been willful and deliberate (Compl. ¶77). This allegation is based on asserted pre-suit knowledge of the patents-in-suit from at least three distinct sources:
    1. Alleged direct communications from Plaintiff's predecessor to Western Digital and/or SanDisk regarding the patent portfolio "in or around 2016" (Compl. ¶53).
    2. Multiple office actions issued by the USPTO starting in April 2016 that cited the ’190 Patent as prior art against a patent application being prosecuted by SanDisk (which Western Digital later acquired) (Compl. ¶73).
    3. A subpoena served on Western Digital in a 2018 International Trade Commission investigation where Plaintiff asserted the ’190 Patent against other parties (Compl. ¶75).

VII. Analyst’s Conclusion: Key Questions for the Case

  • Definitional Scope: A core issue will be whether a memory controller's use of different operational modes for the same physical NAND flash cells (i.e., treating a portion of a TLC drive as an SLC cache) creates distinct "device profiles" as required by the ’190 Patent, or if the claim requires physically distinct memory types.
  • Structural Correspondence: A key factual question will be whether the accused SSDs' LBA-to-PBA mapping tables contain the specific, structured sets of "logical fields" and "PBA fields" that include "access parameters" as claimed in the ’740 Patent, or if they represent a more conventional translation layer where optimization is achieved by separate, unclaimed logic.
  • Knowledge and Intent: A central issue for damages will be Western Digital's state of mind. The court will need to evaluate whether the alleged prior licensing discussions, USPTO citations during prosecution of Western Digital’s own patent applications, and involvement in a prior ITC action establish pre-suit knowledge sufficient to support a finding of willful infringement.