DCT

8:25-cv-00119

Ipvalue Management Inc v. Western Digital Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 8:25-cv-00119, C.D. Cal., 04/09/2025
  • Venue Allegations: Plaintiffs allege venue is proper because Defendants transact business in the Central District of California and have committed acts of infringement in the district, maintaining regular and established places of business, including offices in Irvine, CA.
  • Core Dispute: Plaintiffs allege that Defendants’ 3D NAND flash memory products, including solid-state drives (SSDs), USB flash drives, and memory cards, infringe five patents related to semiconductor memory transistor structure, reference voltage determination methods, and charge pump control circuits.
  • Technical Context: The dispute centers on the fundamental architecture and operation of 3D NAND flash memory, a technology critical for high-density data storage in a wide array of consumer and enterprise electronics.
  • Key Procedural History: The complaint alleges a multi-year history of licensing negotiations, beginning with a letter from IPValue to Western Digital on March 26, 2021, identifying four of the five asserted patents. A subsequent letter on February 10, 2023, identified the fifth patent. The complaint also notes multiple meetings between 2022 and 2024 where infringement evidence was allegedly presented. It is also alleged that on March 7, 2025, Defendant SanDisk filed a complaint for declaratory judgment of noninfringement as to the asserted patents.

Case Timeline

Date Event
2002-10-29 ’505 Patent Priority Date
2005-11-08 U.S. Patent No. 6,963,505 Issues
2007-05-10 ’664 Patent Priority Date
2007-05-25 ’537, ’240, and ’365 Patents Priority Date
2010-03-02 U.S. Patent No. 7,671,664 Issues
2014-01-21 U.S. Patent No. 8,633,537 Issues
2018-03-27 U.S. Patent No. 9,929,240 Issues
2021-03-26 Plaintiff IPValue sends letter to Western Digital identifying ’537, ’240, ’505, and ’664 Patents
2022-09-27 U.S. Patent No. 11,456,365 Issues
2023-02-10 Plaintiff IPValue sends letter to Western Digital identifying ’365 Patent
2025-03-07 Defendant SanDisk files complaint for declaratory judgment of noninfringement
2025-04-09 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,633,537 - "Memory transistor with multiple charge storing layers and a high work function gate electrode"

The Invention Explained

  • Problem Addressed: The patent addresses the problem of poor data retention over time in conventional non-volatile memory transistors. It notes a trade-off where structures with a large initial difference between programmed and erased voltage states often lose charge rapidly, while structures with better retention have a smaller initial performance window, limiting the device’s useful lifetime (’537 Patent, col. 1:47-66).
  • The Patented Solution: The invention proposes a specific multi-layer charge-trapping structure within the transistor, referred to as an "ONNO" (oxide-nitride-nitride-oxide) stack. This stack includes an "oxygen-rich" first nitride layer and an overlying "silicon-rich, oxygen-lean" second nitride layer, which together are designed to improve the program/erase speed and increase the initial voltage window without compromising the long-term charge loss rate (’537 Patent, col. 2:48-60; Fig. 4A).
  • Technical Importance: This layered engineering of the charge-trapping region represented an effort to optimize performance and reliability in scaled flash memory cells, a critical challenge as memory density increased (’537 Patent, col. 2:1-5).

Key Claims at a Glance

  • Independent Claim 17 is asserted in the complaint (Compl. ¶26).
  • Essential elements of claim 17 include:
    • A memory transistor with a vertical channel comprising polysilicon.
    • An ONNO stack disposed about the vertical channel.
    • The ONNO stack comprises:
      • A tunnel dielectric layer abutting the vertical channel.
      • A multi-layer charge-trapping region with a first oxygen-rich nitride layer and a second silicon-rich, oxygen-lean nitride layer.
      • A blocking dielectric layer overlying the multi-layer charge-trapping region.
    • A high work function gate electrode disposed about the ONNO stack.
  • The complaint reserves the right to assert additional claims (Compl. ¶21).

U.S. Patent No. 9,929,240 - "Memory transistor with multiple charge storing layers and a high work function gate electrode"

The Invention Explained

  • Problem Addressed: This patent, from the same family as the ’537 Patent, addresses the same data retention and performance trade-offs in non-volatile memory (’240 Patent, col. 1:50-2:5). It further considers the integration of such memory transistors with standard logic transistors on the same chip, a key feature of System-on-Chip (SOC) applications (’240 Patent, col. 1:16-24).
  • The Patented Solution: The invention claims a semiconductor device that includes both a memory device and a separate metal oxide semiconductor (MOS) logic device. The memory device incorporates a multi-layer charge trapping layer with distinct oxygen-rich and oxygen-lean dielectric layers to manage charge storage and retention. The claimed structure combines this specialized memory cell with a standard logic gate on the same substrate (’240 Patent, col. 2:27-46; Fig. 3).
  • Technical Importance: This approach facilitates the integration of high-performance, non-volatile memory directly with processing logic on a single piece of silicon, which is essential for embedded systems and modern processor design (’240 Patent, col. 1:19-24).

Key Claims at a Glance

  • Independent Claim 12 is asserted in the complaint (Compl. ¶42).
  • Essential elements of claim 12 include:
    • A memory device with a gate structure, a vertical channel, and a multi-layer charge trapping layer.
    • The multi-layer charge trapping layer comprises a first oxygen-rich nitride dielectric layer and a second oxygen-lean nitride dielectric layer.
    • A separate MOS logic device including a gate oxide layer and a second high work function gate electrode.
  • The complaint reserves the right to assert additional claims (Compl. ¶37).

Multi-Patent Capsules

  • Patent Identification: U.S. Patent No. 11,456,365, "Memory transistor with multiple charge storing layers and a high work function gate electrode," issued September 27, 2022.

  • Technology Synopsis: Belonging to the same family as the ’537 and ’240 patents, this patent claims a semiconductor memory device with a vertical channel formed in a substantially annular, or ring-like, shape (’365 Patent, col. 2:50-58). The invention focuses on the geometric arrangement of the channel and the surrounding multi-layer charge storing and dielectric layers, which are also formed in annular shapes to conform to the channel (’365 Patent, col. 2:50-3:5).

  • Asserted Claims: Independent claim 35 is asserted (Compl. ¶56).

  • Accused Features: The complaint alleges that the vertically-oriented, annular-shaped channels and surrounding dielectric layers in Defendants' 3D NAND products infringe this patent (Compl. ¶¶58-62). A cross-sectional micrograph shows the concentric annular layers of the accused device (Compl. ¶58, p. 20).

  • Patent Identification: U.S. Patent No. 6,963,505, "Method circuit and system for determining a reference voltage," issued November 8, 2005.

  • Technology Synopsis: This patent addresses the problem of "voltage drift" in non-volatile memory cells, where the threshold voltage required to read a cell's state changes over time due to charge leakage or other interference, leading to read errors (’505 Patent, col. 2:28-32). The invention provides a method for dynamically determining an optimal reference voltage by reading a set of cells with multiple possible reference levels, determining the read error rate for each level, and selecting the level with a "relatively low" error rate to use for subsequent read operations (’505 Patent, col. 4:1-18; Fig. 3).

  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶71).

  • Accused Features: The complaint alleges that Defendants' "smart Vth tracking read" (SVTR) technology, which adaptively finds an optimal read voltage to minimize the bit error rate, infringes the claimed method (Compl. ¶¶76-78).

  • Patent Identification: U.S. Patent No. 7,671,664, "Charge pump control circuit and method," issued March 2, 2010.

  • Technology Synopsis: This patent describes a control circuit for a charge pump, which is used to generate voltages higher than the power supply voltage, a necessary function for programming and erasing flash memory. The problem addressed is balancing fast start-up times with low power consumption during steady-state operation (’664 Patent, col. 1:26-40). The patented solution is a clock control circuit that uses a high-frequency clock for rapid voltage ramp-up during startup and then switches to a low-frequency clock for power efficiency during normal operation, with the switchover controlled based on a "dynamic load" (’664 Patent, col. 2:48-61).

  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶87).

  • Accused Features: The complaint alleges that control circuits within Defendants' 3D NAND flash memory products, which manage the charge pump clock frequency based on operational load, infringe the patent (Compl. ¶¶88-89).

III. The Accused Instrumentality

  • Product Identification: The "Accused Products" are broadly defined as Defendants' SSDs, OptiNAND HDDs, USB Flash Drives, Embedded Flash, and Memory Cards that contain 3D NAND flash memory (Compl. ¶21). The complaint specifically references a Western Digital SA530 SSD as an exemplary product (Compl. ¶29, p. 10).
  • Functionality and Market Context: The complaint alleges the Accused Products incorporate 3D NAND flash memory chips, including those with 96-layer and 112-layer technology, some of which were allegedly developed via a joint venture between Toshiba and SanDisk (Compl. ¶¶72, 74). The infringement allegations focus on two aspects:
    • Physical Structure: The microscopic physical structure of the memory transistors, specifically the vertical, annular polysilicon channels and the composition of the surrounding multi-layer dielectric stacks used for charge trapping (Compl. ¶¶28-33). The complaint presents a micrograph of an accused product's memory array, showing vertical channels and gates (Compl. ¶27, p. 9).
    • Operational Methods: The methods and circuits used to operate the memory, including the "smart Vth tracking read" (SVTR) process for optimizing read voltages and the charge pump control circuits that manage internal operating voltages (Compl. ¶¶76, 88). A diagram from a technical paper is used to illustrate the SVTR process allegedly used in the products (Compl. ¶78, p. 30).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,633,537 Infringement Allegations

Claim Element (from Independent Claim 17) Alleged Infringing Functionality Complaint Citation Patent Citation
a memory transistor including: a vertical channel comprising polysilicon extending from a first diffusion region... to a second diffusion region... The Accused Products allegedly include a memory transistor with a vertical channel made of polysilicon that connects diffusion regions. This is supported by a cross-sectional micrograph showing "top" and "bottom" vertical channels (Compl. ¶28, p. 9). ¶28 col. 10:46-51
an oxide-nitride-nitride-oxide (ONNO) stack disposed about the vertical channel, the ONNO stack comprising: a tunnel dielectric layer abutting the vertical channel; The products allegedly feature an ONNO stack around the vertical channel, which includes a tunnel dielectric layer ("Tunnel Oxide") directly adjacent to the silicon channel ("Si Channel"). A micrograph shows these concentric layers (Compl. ¶29-30, p. 10). ¶¶29-30 col. 10:52-54
a multi-layer charge-trapping region including a first nitride layer comprising an oxygen-rich nitride abutting the tunnel dielectric layer, and a second nitride layer comprising a silicon-rich, oxygen-lean nitride overlying the first nitride layer; The "Charge Trap Layer" in the accused ONNO stack is alleged to be a multi-layer region meeting these specific compositional requirements. ¶31 col. 9:5-8
a blocking dielectric layer overlying the multi-layer charge-trapping region; and The accused ONNO stack allegedly includes an outer "Blocking Oxide" layer over the charge trap region, as shown in the provided micrograph (Compl. ¶32, p. 12). ¶32 col. 10:55-56
a high work function gate electrode disposed about the ONONO stack, abutting the blocking dielectric layer. The Accused Products allegedly include a high work function gate electrode (labeled "W" for tungsten in a micrograph) disposed around the ONNO stack, next to the blocking dielectric layer (Compl. ¶33, p. 13). ¶33 col. 10:57-59
  • Identified Points of Contention:
    • Scope Questions: A central question will be whether the materials used in the accused "Charge Trap Layer" meet the claim definitions of "oxygen-rich nitride" and "silicon-rich, oxygen-lean nitride." This may depend on evidence regarding the precise elemental composition and stoichiometry of the layers in Defendants' products.
    • Technical Questions: What evidence does the complaint provide, beyond labeled micrographs, that the distinct chemical compositions required by the "multi-layer charge-trapping region" element are actually present in the Accused Products? The resolution will likely require detailed materials science analysis.

U.S. Patent No. 9,929,240 Infringement Allegations

Claim Element (from Independent Claim 12) Alleged Infringing Functionality Complaint Citation Patent Citation
a semiconductor device, comprising: a memory device including: a gate structure including a first high work function gate electrode; The Accused Products are alleged to be semiconductor devices containing a memory device with a gate structure. A micrograph shows a gate electrode made of tungsten ("W"), identified as a high work function material (Compl. ¶44, p. 16). ¶¶43-44 col. 4:5-11
a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, wherein the channel is vertical... The memory device allegedly includes a vertical channel connecting diffusion regions. This is supported by a micrograph showing the vertical structure of the polysilicon channel (Compl. ¶45, p. 16). ¶45 col. 4:12-14
a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel, wherein the multi-layer charge trapping layer comprises a first dielectric layer...including oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride The Accused Products allegedly contain a multi-layer stack between the gate and channel with these specific layers. A micrograph illustrates the "Tunnel Oxide," "Charge Trap Layer," and "Blocking Oxide" (Compl. ¶46, p. 17). ¶46 col. 4:15-26
a metal oxide semiconductor (MOS) logic device including a gate oxide layer and a second high work function gate electrode disposed thereon. The complaint alleges the Accused Products contain memory controllers or other components that constitute a MOS logic device, which is separate from the memory array but integrated on the same semiconductor device. ¶47 col. 4:27-30
  • Identified Points of Contention:
    • Scope Questions: Does the accused product contain a distinct "MOS logic device" as required by the claim, separate from the memory array itself? The analysis may turn on whether on-chip memory controllers or other peripheral circuits meet the claim's definition of a "logic device."
    • Technical Questions: As with the ’537 patent, a key technical question will be whether the accused charge trapping layer has the specific two-part, compositionally distinct structure ("oxygen-rich" vs. "oxygen-lean") required by the claim.

V. Key Claim Terms for Construction

  • For the ’537 Patent:

    • The Term: "multi-layer charge-trapping region including a first nitride layer comprising an oxygen-rich nitride... and a second nitride layer comprising a silicon-rich, oxygen-lean nitride" (claim 17).
    • Context and Importance: This term is the core of the invention. The infringement case hinges on whether the specific material composition of Defendants' charge trap layers falls within this definition. Practitioners may focus on this term because the distinction between "oxygen-rich" and "silicon-rich, oxygen-lean" is a technical limitation that may not be met by all multi-layer nitride structures.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the layers in functional terms, stating the goal is to create deep traps to reduce charge loss, which could support an argument that any structure achieving this function meets the spirit of the claim (’537 Patent, col. 6:39-47).
      • Evidence for a Narrower Interpretation: The specification provides specific exemplary process conditions for creating these layers, such as using BTBAS gas to increase the carbon level and create "trap-rich" oxynitride, suggesting the terms may be tied to particular material properties achieved through these methods (’537 Patent, col. 5:35-51).

  • For the ’240 Patent:

    • The Term: "a metal oxide semiconductor (MOS) logic device" (claim 12).
    • Context and Importance: This term distinguishes the claimed invention from a device containing only memory cells. Infringement requires the presence of both the specialized memory device and a separate MOS logic device. The dispute may turn on whether peripheral circuits on the memory chip, such as controllers or decoders, qualify as a "MOS logic device" under the patent's definition.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The background discusses "System-On-Chip (SOC) applications" where memory and logic are combined, suggesting the term could broadly cover any standard logic transistor integrated on the same substrate as the memory (’240 Patent, col. 1:19-24). The specification also states the invention enables fabrication of "both memory and logic transistors" (’240 Patent, col. 3:17-18).
      • Evidence for a Narrower Interpretation: The detailed description contrasts the "memory transistor 304" with the "logic transistor 302," depicting them as distinct structures with potentially different gate electrodes, which could support a narrower reading that requires a clearly delineated, separate logic section, not just integrated peripheral circuitry (’240 Patent, col. 7:35-44; Fig. 3).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement and contributory infringement for all five patents, asserting that Defendants knew their components were especially adapted for use in infringement and not staple articles of commerce (e.g., Compl. ¶¶21-22, 37-38). The allegations are based on Defendants' knowledge of the patents from Plaintiffs' communications.
  • Willful Infringement: Willfulness is alleged for all five patents based on pre-suit knowledge. The complaint alleges Western Digital knew of the ’537, ’240, ’505, and ’664 patents as of March 26, 2021, and of the ’365 patent as of February 10, 2023, via letters and subsequent meetings where infringement was discussed (Compl. ¶¶13-15). It is alleged that SanDisk had knowledge as a successor-in-part and through its own confirmed awareness of the allegations, evidenced by its declaratory judgment action (Compl. ¶16).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A central issue will be one of compositional scope: can Plaintiffs prove that the dielectric layers in Defendants' mass-produced 3D NAND devices possess the specific, distinct "oxygen-rich" and "silicon-rich, oxygen-lean" nitride compositions required by the asserted claims of the ’537, ’240, and ’365 patents, or will discovery reveal a technical mismatch?
  2. A key question of functional equivalence will arise for the ’505 patent: does the accused "smart Vth tracking read" (SVTR) algorithm, which adaptively finds an optimal read voltage, operate in a manner that maps onto the claimed steps of testing a set of possible reference levels and selecting one based on a "relatively low" error rate?
  3. For the ’664 patent, the case may turn on a question of operational scope: does the accused charge pump's method of switching between clock frequencies meet the specific limitation of being based on a "dynamic load," and how will that term be construed in the context of the patent's disclosure?