DCT
2:22-cv-01510
Bell Semiconductor LLC v. Kioxia America Inc
Key Events
Amended Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Kioxia America, Inc. (California) and Kioxia Corp (Japan)
- Plaintiff’s Counsel: McKool Smith, P.C.; Law Offices of Seth Wiener; Devlin Law Firm LLC
- Case Identification: 2:22-cv-01510, E.D. Cal., 11/14/2022
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of California because Defendant Kioxia maintains a regular and established place of business in Folsom, CA, where it allegedly employs engineers and performs infringing circuit design and validation activities.
- Core Dispute: Plaintiff alleges that Defendant’s processes for designing and validating semiconductor devices, and the resulting products, infringe patents related to efficient electronic design automation (EDA) methodologies for error checking and manufacturing preparation.
- Technical Context: The technology concerns software methods used in semiconductor design to improve manufacturing yield and reduce design cycle time, specifically by optimizing how design rule checks are performed and how "dummy fill" is managed after late-stage design changes.
- Key Procedural History: The operative pleading is a First Amended Complaint. The complaint does not mention any prior litigation, inter partes review (IPR) proceedings, or licensing history related to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2003-10-10 | ’803 Patent Priority Date |
| 2004-09-22 | ’989 Patent Priority Date |
| 2006-12-12 | ’989 Patent Issue Date |
| 2007-08-21 | ’803 Patent Issue Date |
| 2022-11-14 | First Amended Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,149,989 - "Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design," issued December 12, 2006
The Invention Explained
- Problem Addressed: The patent's background describes the inefficiency of conventional semiconductor design validation. Performing validation checks late in the process, after a design is complete, means that discovering a fault like a short circuit can force a costly and time-consuming reset of the design schedule (Compl. ¶26; ’989 Patent, col. 2:41-46). Conversely, running a full validation check early on an incomplete design generates a large number of false errors, which are difficult to sort through (Compl. ¶26; ’989 Patent, col. 2:54-58).
- The Patented Solution: The invention proposes a method for effective early-stage validation. Instead of using a comprehensive set of rules, the method generates a "specific rule deck" that contains only the rules needed to identify a particular class of errors: "texted metal short circuits" between different signal sources, power, and ground (Compl. ¶28; ’989 Patent, Abstract). This targeted approach allows designers to find critical flaws early in the process without being overwhelmed by false positives from the incomplete parts of the design (Compl. ¶27; ’989 Patent, col. 2:64-3:11).
- Technical Importance: By enabling focused, early-stage error detection, the method aimed to reduce computer processing time, avoid late-stage design resets, and shorten the overall product development cycle (Compl. ¶8; ’989 Patent, col. 3:7-11).
Key Claims at a Glance
- The complaint asserts independent claim 1.
- Claim 1 recites a method comprising the essential steps of:
- (a) receiving as input a representation of an integrated circuit design;
- (b) receiving as input a physical design rule deck that specifies rule checks;
- (c) generating a specific rule deck from the physical design rule deck, where the specific deck includes only rules for "texted metal short circuits" between different signal sources, power, and ground; and
- (d) performing a physical design validation on the design using the specific rule deck to identify those short circuits.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 7,260,803 - "Incremental Dummy Metal Insertions," issued August 21, 2007
The Invention Explained
- Problem Addressed: In semiconductor fabrication, Chemical Mechanical Planarization (CMP) requires a uniform density of material across the chip's surface. To achieve this, "dummy metal" is added to sparse areas. The patent notes that if a design is changed late in the process via an Engineering Change Order (ECO), the conventional approach was to discard all the previously placed dummy metal and rerun the entire time-consuming "dummy fill" process, which could delay a project by 30 hours or more for each change (Compl. ¶¶ 3, 35; ’803 Patent, col. 1:51-65).
- The Patented Solution: The patent discloses an "incremental" method to avoid this inefficiency. After a design change is made, the process does not start over. Instead, it performs a check to see if any of the existing dummy metal objects now intersect with any other design objects due to the change. If an intersection is found, the method simply deletes the specific intersecting dummy metal objects, leaving the rest untouched and "thereby avoiding having to rerun the dummy fill tool" (Compl. ¶¶ 4, 37; ’803 Patent, Abstract, col. 2:7-14).
- Technical Importance: This innovation sought to save significant time and cost in the final stages of chip design by allowing for late-stage modifications without requiring a complete, computationally expensive rerun of the dummy fill procedure (Compl. ¶¶ 5, 36; ’803 Patent, col. 2:21-23).
Key Claims at a Glance
- The complaint asserts independent claim 1.
- Claim 1 recites a method for performing dummy metal insertion, comprising the essential steps of:
- (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; and
- (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool.
- The complaint does not explicitly reserve the right to assert dependent claims.
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Processes" as the semiconductor design, validation, and manufacturing methodologies used by Kioxia (Compl. ¶¶ 45, 58). These processes are alleged to employ third-party EDA tools from vendors like Cadence, Synopsys, and/or Siemens (Compl. ¶¶ 45, 58). The physical products resulting from these processes are identified as Kioxia's devices, with the "XG7 NVMe 512GB SSD" cited as a specific example (Compl. ¶¶ 44, 57).
Functionality and Market Context
- The complaint alleges that Kioxia's design processes for products like the XG7 SSD perform the patented methods. Specifically, for the ’989 Patent, Kioxia is alleged to use tools with "short finder" or "short locator" functionality to identify texted metal short circuits (Compl. ¶47). For the ’803 Patent, Kioxia is alleged to use tools that, after an Engineering Change Order (ECO), perform a Design Rule Check (DRC) and "repair" violations by trimming or deleting intersecting dummy metal fill (Compl. ¶¶ 59-60).
- The complaint alleges Kioxia derives substantial revenues from its infringing activities, which include designing, manufacturing, and selling products in the United States that are made using the Accused Processes (Compl. ¶21).
- No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’989 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input a representation of an integrated circuit design; | Kioxia imports a circuit design for its XG7 NVMe 512GB SSD into an EDA tool from Cadence, Synopsys, and/or Siemens. | ¶45 | col. 7:10-12 |
| (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; | Kioxia's EDA tools receive various "in-design verification processes" for physical design and verification. | ¶46 | col. 7:13-16 |
| (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits...; | Kioxia employs an EDA tool that includes a "short finder," "short locator," or similar functionality that allows designers to select and identify texted metal short circuits. | ¶47 | col. 7:17-24 |
| (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits... | The tool performs a validation that identifies texted metal short circuits between ground, power, and other signal nets based on the selected rules. | ¶47 | col. 8:1-6 |
- Identified Points of Contention:
- Scope Question: A primary issue may be whether the accused "short finder" or "short locator" functionality constitutes "generating a specific rule deck" that includes "only" the specified rules, as required by claim 1(c). The court may need to determine if a feature that filters or selects rules from a larger set is equivalent to generating a new, distinct, and limited rule deck.
- Technical Question: What evidence will show that Kioxia's process uses a subset of rules specifically for early-stage validation, as emphasized in the patent's specification? The infringement allegations focus on the tool's capability but are less specific about when in the design flow this capability is used.
’803 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| ...a method for performing dummy metal insertion in design data for an integrated circuit, which includes dummy metal objects inserted by a dummy fill tool... | Kioxia's process for its XG7 SSD layout uses an "integrated" or "in-design" flow that inserts dummy metal objects. | ¶58 | col. 5:6-8 |
| (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; | After an Engineering Change Order (ECO) is received, Kioxia employs a tool to perform a Design Rule Check (DRC) to identify rule violations, including those related to metal fill geometries. | ¶59 | col. 5:9-12 |
| (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool. | Kioxia uses a tool that "repairs DRC violations" by, for example, allowing designers to "trim metal fill geometries that cause the short or DRC violation." | ¶60 | col. 5:13-16 |
- Identified Points of Contention:
- Scope Question: Does performing a general "Design Rule Check (DRC)," as alleged in the complaint, meet the more specific claim requirement of "performing a check to determine whether any dummy metal objects intersect with any other objects"? The infringement argument may depend on whether a general DRC is proven to necessarily include this specific check.
- Technical Question: The complaint alleges the accused process involves "trim[ming] metal fill geometries," while the claim requires "deleting the intersecting dummy metal objects." The case may turn on whether modifying or trimming an object is technically and legally equivalent to deleting the entire object as claimed.
V. Key Claim Terms for Construction
’989 Patent: "generating a specific rule deck ... wherein the specific rule deck includes only physical design rules that are specific to..."
- Context and Importance: This term is central to the inventive concept of the ’989 Patent. The infringement analysis will hinge on whether Kioxia’s alleged use of a "short finder" function within a larger EDA tool constitutes "generating" a new, limited deck, or is merely a filtering operation outside the scope of the claim.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification emphasizes the goal of reducing run time by avoiding a full rule check, stating the invention provides "design rules that may be used... in an early stage... to detect design rule violations" (’989 Patent, col. 2:64-3:3). A party could argue that any process that results in only the specific rules being applied for a validation run, regardless of whether a new file is created, achieves this goal and falls within the meaning of "generating."
- Evidence for a Narrower Interpretation: The claim language recites "generating a specific rule deck" as an affirmative step (’989 Patent, col. 7:17-18). A party may argue this requires the creation of a new, discrete data object or file that contains only the specified rules, and that simply selecting or filtering rules for application from a pre-existing, comprehensive deck is not "generating" a new one.
’803 Patent: "deleting the intersecting dummy metal objects"
- Context and Importance: This term is critical because the complaint alleges the accused process "repairs" violations by "trim[ming] metal fill geometries" (Compl. ¶60). Practitioners may focus on this term because the distinction between modifying ("trimming") an object and removing ("deleting") it could be dispositive of infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's overall purpose is to "avoid[] having to rerun the dummy fill tool" after a change (’803 Patent, Abstract). A party could argue that trimming the portion of a dummy metal object that causes an intersection accomplishes the same goal as deleting the entire object, and thus "trimming" should be considered a form of "deleting" in this context.
- Evidence for a Narrower Interpretation: The claim recites "deleting the intersecting dummy metal objects" (plural) (’803 Patent, col. 5:13-14). A party may argue this requires the removal of the entire data object from the design, not merely altering its shape. The patent flowchart also shows a step to "Delete the object" as a discrete action following an intersection check (’803 Patent, Fig. 2, box 114).
VI. Other Allegations
- Indirect Infringement: The complaint makes passing references to infringement under 35 U.S.C. § 271, et seq. (Compl. ¶¶ 49, 62), but it does not plead separate counts for indirect infringement or allege specific facts to support the knowledge and intent elements required for induced or contributory infringement. The allegations focus on Kioxia's direct infringement through its own design processes.
- Willful Infringement: The complaint alleges that Kioxia's infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶¶ 50, 63). However, it does not explicitly plead willfulness or allege any facts indicating Kioxia had pre-suit knowledge of the patents-in-suit. Any claim for enhanced damages would likely depend on conduct occurring after the filing of the complaint.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of process equivalence: Does Kioxia’s alleged use of general-purpose EDA tools with "short finder" or "DRC repair" functionalities meet the specific, multi-step method claims of the patents? The court will likely have to decide if a standard filtering or trimming feature is equivalent to the claimed "generating a specific rule deck" (’989 patent) and "deleting the intersecting dummy metal objects" (’803 patent).
- A key question will be one of definitional scope: Can the term "deleting" in the context of the ’803 patent be construed to cover the act of "trimming" a geometry as alleged in the complaint? Similarly, does the phrase "generating a specific rule deck" in the ’989 patent require the creation of a new data file, or can it encompass the in-memory selection of rules for a specific validation run?
- An underlying evidentiary question will be one of implementation: Beyond the capabilities of the third-party EDA tools, what evidence will be presented to show how Kioxia actually configures and uses these tools in its day-to-day design flow? Proving infringement will likely require demonstrating that Kioxia's internal processes align with the specific timing and logical steps recited in the patent claims.