Bell Semiconductor LLC v. Kioxia America Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Bell Semiconductor, LLC (Delaware)
  • Defendant: Kioxia America, Inc. (California) and Kioxia Corporation (Japan)
  • Plaintiff’s Counsel: Law Offices of Seth Wiener; McKool Smith, P.C.; Devlin Law Firm LLC
• Case Identification: 2:22-cv-01880, E.D. Cal., 11/23/2022
• Venue Allegations: Plaintiff alleges venue is proper based on Defendant Kioxia having a regular and established place of business in the district, specifically a Folsom, California office where it employs engineers and advertises for relevant positions such as "ASIC Design Engineer."
• Core Dispute: Plaintiff alleges that Defendant’s processes for designing and manufacturing semiconductor devices, including specific SSD controller chips, infringe two patents related to integrated circuit (IC) design and fabrication methodologies.
• Technical Context: The lawsuit concerns semiconductor electronic design automation (EDA), focusing on methods to improve efficiency in revising IC layouts and to ensure physical uniformity during the manufacturing process.
• Key Procedural History: The operative pleading is a First Amended Complaint. The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
2000-01-18	U.S. Patent No. 6,436,807 Priority Date
2002-08-20	U.S. Patent No. 6,436,807 Issue Date
2004-12-17	U.S. Patent No. 7,231,626 Application Filing / Priority Date
2007-06-12	U.S. Patent No. 7,231,626 Issue Date
2022-11-23	Complaint Filing Date (First Amended Complaint)

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,231,626 - Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows (Issued Jun. 12, 2007)

The Invention Explained

• Problem Addressed: The patent’s background section describes that conventional methods for implementing an engineering change order (ECO) in an IC design are highly inefficient because design tools for tasks like cell placement and routing must be run for the entire circuit, even for a minor modification (Compl. ¶28; ’626 Patent, col. 2:15-22). This process could take a week, regardless of the change's size, creating a significant bottleneck (Compl. ¶29; ’626 Patent, col. 2:37-44).
• The Patented Solution: The invention proposes a method to localize the impact of an ECO by creating a "window"—a bounded area smaller than the entire circuit—that encloses the design change. Subsequent process steps, such as routing and design rule checks, are performed only on the nets contained within this window. The results from this incremental process are then merged back into the full design, dramatically reducing the time and computational resources required (Compl. ¶¶ 4, 30; ’626 Patent, col. 3:19-23). The process is illustrated in the patent's flow chart in Figure 6 (Compl. Ex. A, Fig. 6).
• Technical Importance: This "windowing" approach provided a more scalable and efficient methodology for making late-stage design changes, a critical capability for managing the increasing complexity of modern ICs without delaying time-to-market (Compl. ¶¶ 31-32).

Key Claims at a Glance

• The complaint asserts infringement of at least Claim 1 (Compl. ¶¶ 34, 50).
• Independent Claim 1 requires a method with the following key steps:
  • Receiving an integrated circuit design and an engineering change order.
  • Creating at least one "window" that encloses the change, where the window is smaller than the entire area of the circuit design.
  • Performing an "incremental routing" of the design only for each net enclosed by the window.
  • Replacing an area in a copy of the design with the results of the incremental routing to generate a revised design.
  • Generating the revised integrated circuit design as output.

U.S. Patent No. 6,436,807 - Method for Making an Interconnect Layer and a Semiconductor Device Including the Same (Issued Aug. 20, 2002)

The Invention Explained

• Problem Addressed: The patent addresses a problem in semiconductor manufacturing related to Chemical Mechanical Planarization (CMP), a process for smoothing layers. The patent’s background explains that variations in the density of metal features on a layer can cause uneven polishing, creating defects (’807 Patent, col. 1:67-2:2; Compl. ¶¶ 5, 40). Prior art methods added "dummy fill" to sparse areas based on a fixed density, which often resulted in adding unnecessary material that could increase parasitic capacitance and degrade device performance (’807 Patent, col. 2:17-21, 2:31-33; Compl. ¶6).
• The Patented Solution: The invention claims a more intelligent method for adding dummy fill. The process first involves "determining an active interconnect feature density" for various regions of the layout. Then, it adds dummy fill to each region specifically to achieve a "desired density," thereby avoiding unnecessary fill. Crucially, the method comprises "defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias" to ensure the fill itself does not cause manufacturing issues (’807 Patent, Abstract; Compl. ¶¶ 8, 42). Figure 3 of the patent provides a high-level flowchart of this process (’807 Patent, Fig. 3).
• Technical Importance: This technique allows for achieving a more uniform surface for planarization, which is critical for manufacturing yield, while simultaneously minimizing the addition of performance-degrading parasitic capacitance (Compl. ¶9; ’807 Patent, col. 4:50-54).

Key Claims at a Glance

• The complaint asserts infringement of at least Claim 1 (Compl. ¶¶ 42, 64).
• Independent Claim 1 requires a method for making a layout with the following key steps:
  • Determining an active interconnect feature density for each of a plurality of layout regions.
  • Adding dummy fill features to each layout region to obtain a desired density of active and dummy features.
  • Wherein the adding step comprises defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a layer to be deposited over the interconnect layer.

III. The Accused Instrumentality

Product Identification

• The complaint identifies the "Kioxia Accused Product" as the TC58NC0L1XGSD PCIe Gen 4.0 NVMe SSD Controller chip (Compl. ¶10). More broadly, the infringement allegations are directed at the "Accused Processes," which are the design and manufacturing methodologies Kioxia allegedly uses to develop and fabricate its semiconductor devices (Compl. ¶¶ 50, 64).

Functionality and Market Context

• The accused functionalities are not end-user features of the SSD controller but are internal processes used during its design and fabrication. The complaint alleges Kioxia utilizes EDA tools from vendors like Cadence, Synopsys, and/or Siemens to perform these processes (Compl. ¶¶ 50, 64). The complaint alleges Kioxia derives "substantial revenues" from its infringing activities but does not provide specific market data for the accused product (Compl. ¶22).

IV. Analysis of Infringement Allegations

The complaint alleges that Kioxia’s use of certain EDA tools to design and fabricate its SSD controllers constitutes direct infringement of the asserted patents. The complaint references, but does not include, expert declarations and exemplary infringement analyses that it states further describe the infringement (Compl. ¶¶ 53, 67, 10, 12). No probative visual evidence provided in complaint.

’626 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
(c) creating at least one window in the integrated circuit design that encloses a change ... wherein the window ... define an area that is less than an entire area...	Kioxia’s Accused Processes allegedly perform a method for "only routing the nets affected by the ECO and merging that changed area," which is alleged to meet the "window" limitation.	¶50	col. 3:59-62
(d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window;	Kioxia allegedly "employs a variety of design tools... to perform incremental routing in implementing an ECO," and performs parasitic extraction and design rule checks only for nets in the window.	¶¶50-52	col. 4:5-18
(e) replacing an area in a copy of the integrated circuit design ... with results of the incremental routing to generate a revised integrated circuit design; and	Kioxia's process allegedly involves "merging that changed area into the overall circuit layout... to generate a revised integrated circuit design."	¶50	col. 4:20-24

• Identified Points of Contention:
  • Evidentiary Question: The complaint's allegations are made "on information and belief" and rely on proving that the specific functions of third-party EDA tools, as used by Kioxia, perform the claimed steps. A central issue may be whether discovery yields evidence that Kioxia's workflow directly maps to the claim limitations, such as the specific method of creating a "window" and performing "incremental routing" as defined in the patent.
  • Scope Question: A potential dispute may arise over whether Kioxia’s method of localizing a design change is coextensive with the "window" concept as claimed. The defense could argue that its process is a technically distinct optimization that does not meet the specific structural and functional requirements of the claims.

’807 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
(a) determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout; and	Kioxia allegedly uses a design tool "to determine an active interconnect feature density for each of a plurality of layout regions of the interconnect layout of its Accused Product."	¶65	col. 6:52-56
(b) adding dummy fill features to each layout region to obtain a desired density ... the adding comprising defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias...	Kioxia's design tools allegedly "add dummy fill features to each layout region to obtain a desired density" and this process "comprises defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias."	¶¶66-67	col. 6:1-10

• Identified Points of Contention:
  • Technical Question: The complaint asserts that Kioxia’s process defines dummy fill dimensions "based upon a dielectric layer deposition bias." A key factual question will be whether Kioxia’s process actually uses this specific physical parameter as an input for its algorithm, or if it relies on other, non-infringing criteria to determine dummy fill rules.
  • Scope Question: The construction of "dielectric layer deposition bias" will be critical. The patent provides a specific technical meaning related to physical protrusions formed during deposition. The dispute may turn on whether Kioxia’s algorithm, even if it accounts for layer properties, uses the specific "bias" contemplated by the patent.

V. Key Claim Terms for Construction

Term from ’626 Patent: "window"

• Context and Importance: This term is central to the invention's point of novelty. The outcome of the infringement analysis may depend on whether Kioxia's method of isolating design changes falls within the scope of a "window."
• Intrinsic Evidence for a Broader Interpretation: The specification provides a high-level definition of "window" as "a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 3:59-62). Plaintiff may argue this broad, functional definition covers any method of localizing ECOs.
• Intrinsic Evidence for a Narrower Interpretation: The detailed description teaches a specific method for creating the window by calculating and merging "bounding box[es]" around changed port instances (’626 Patent, col. 4:57-col. 5:10). Defendant may argue that the term should be limited to this more specific embodiment.

Term from ’807 Patent: "based upon a dielectric layer deposition bias"

• Context and Importance: This phrase qualifies the "adding dummy fill" step and is a key distinction from prior art methods that used generic density targets. Infringement of Claim 1 hinges on whether Kioxia's process uses this specific input. Practitioners may focus on this term because it links a design rule to a specific physical manufacturing characteristic.
• Intrinsic Evidence for a Broader Interpretation: The plain language of the claim could be argued to cover any process that considers the deposition bias as one of several factors in determining the dummy fill dimensions.
• Intrinsic Evidence for a Narrower Interpretation: The specification describes "bias" in detail as a physical phenomenon, such as "negative bias" from an HDP-CVD process where a protrusion's width is less than the underlying feature (’807 Patent, col. 2:42-48). It further quantifies a relationship, suggesting the lateral dimension should be "at least twice an absolute value of the negative dielectric layer deposition bias" (’807 Patent, col. 5:20-24). Defendant may argue the term requires this specific physical and mathematical basis.

VI. Other Allegations

• Indirect Infringement: The complaint primarily alleges direct infringement by Kioxia through its use of the patented methods (Compl. ¶¶ 49, 63). It also includes allegations related to making, selling, and importing products manufactured using the accused processes, which may implicate infringement under 35 U.S.C. § 271(g) (Compl. ¶¶ 55, 69). The complaint does not plead facts to support claims of induced or contributory infringement.
• Willful Infringement: The complaint does not use the term "willful" but alleges that Kioxia's infringement is "exceptional" and seeks attorneys' fees pursuant to 35 U.S.C. § 285 (Compl. ¶¶ 56, 70). The complaint does not allege any facts regarding pre-suit knowledge of the patents or other egregious conduct that would typically support such a finding.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of evidentiary proof: can the Plaintiff, through discovery, establish that the internal design and fabrication workflows at Kioxia, which utilize complex third-party EDA software, in fact practice the specific steps recited in the asserted claims? The complaint’s reliance on "information and belief" highlights that the case will likely turn on evidence obtained from the Defendant.
• The case will also present a key question of claim construction and technical mapping: for the ’807 patent, can the phrase "based upon a dielectric layer deposition bias" be construed to read on the algorithm Kioxia uses to place dummy fill, or will discovery reveal that Kioxia's methodology is based on different, non-infringing technical parameters?
• Finally, for the ’626 patent, a central question will be one of functional equivalence: does the accused process for localizing design changes in Kioxia’s workflow represent the same inventive "windowing" method claimed by the patent, or is it a fundamentally different optimization technique that falls outside the claim scope?