DCT

3:02-cv-00637

Broadcom Corp v. Intel Corp

Key Events

Complaint

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: Broadcom Corporation (California)
- Defendant: Intel Corporation (Delaware)
- Plaintiff’s Counsel: Wilson Sonsini Goodrich & Rosati
Case Identification: 3:02-cv-00637, N.D. Cal., 02/06/2002
Venue Allegations: Venue is alleged to be proper in the Northern District of California because Defendant Intel Corporation resides and maintains its principal place of business in the district.
Core Dispute: Plaintiff Broadcom seeks a declaratory judgment that its products do not infringe any valid claims of four U.S. patents owned by Defendant Intel related to single-instruction multiple-data (SIMD) processing, pipelined video encoding, DMA control structures, and variable length code decoding.
Technical Context: The patents-in-suit concern fundamental aspects of high-performance microprocessor architecture and multimedia data processing, technologies central to the semiconductor industry.
Key Procedural History: The complaint states that this action arises from a charge of infringement made by Intel against Broadcom in a separate litigation. Specifically, Intel filed a motion to amend its complaint in the U.S. District Court for the District of Delaware on or about January 7, 2001, to assert the patents-in-suit against Broadcom, creating the "actual and justiciable controversy" alleged to be necessary for this declaratory judgment action.

Case Timeline

Date	Event
1991-10-24	’370 Patent Priority Date
1993-05-26	’399 Patent Priority Date
1994-11-01	’370 Patent Issue Date
1995-03-03	’784 Patent Priority Date
1996-11-12	’887 Patent Priority Date
1997-01-07	’399 Patent Issue Date
1997-07-01	’784 Patent Issue Date
1998-10-13	’887 Patent Issue Date
2001-01-07	Intel moves to amend complaint in Delaware litigation to charge Broadcom with infringement
2002-02-06	Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,821,887 - "Method and Apparatus for Decoding Variable Length Codes"

The Invention Explained

Problem Addressed: The patent describes that prior art methods for decoding variable length codes (VLCs), such as Huffman codes used in video compression, often rely on a single, large lookup table (Compl. Ex. A, '887 Patent, col. 3:51-54). In computer systems with a cache memory hierarchy, accessing such a large table can be inefficient, leading to frequent "cache misses" that slow down processing as data is fetched from slower main memory ('887 Patent, col. 3:55-61).
The Patented Solution: The invention proposes a more cache-efficient, two-level table structure for decoding. It uses a small "major table" that contains entries for the most frequently occurring VLCs and a larger "minor table" for less common ones ('887 Patent, Abstract). A decoding process first checks the small, fast major table; if the code is not found (a "miss"), it then proceeds to the minor table ('887 Patent, col. 4:18-28).
Technical Importance: This architectural approach aims to improve the performance of real-time decoding operations, particularly for multimedia, by tailoring the data access pattern to the memory hierarchy of modern processors.

Key Claims at a Glance

The complaint, being one for declaratory judgment, does not identify specific claims asserted by Intel. It seeks a declaration of non-infringement of "any valid claim" of the patents-in-suit (Compl. ¶1; Prayer for Relief ¶a).

U.S. Patent No. 5,592,399 - "Pipelined Video Encoder Architecture"

The Invention Explained

Problem Addressed: The patent notes that hardware for video encoding and decoding operations was often expensive, slow, and inflexible. Performing the multiple necessary steps, such as filtering, frame differencing, and transforms, in a serial fashion created processing bottlenecks ('399 Patent, col. 1:11-23).
The Patented Solution: The invention describes a pipelined hardware architecture where distinct video processing operations are performed simultaneously on different, contiguous data values ('399 Patent, Abstract). For example, a frame differencing device can operate on one data value at the same time a discrete cosine transform device operates on a second data value and a loop filter operates on a third, creating an assembly-line effect that increases throughput ('399 Patent, col. 3:1-11).
Technical Importance: This pipelined approach is designed to accelerate video compression and decompression, a critical requirement for enabling real-time applications like video conferencing on computer systems.

Key Claims at a Glance

The complaint does not identify specific claims asserted by Intel. It seeks a declaration of non-infringement of "any valid claim" of the patents-in-suit (Compl. ¶1; Prayer for Relief ¶a).

U.S. Patent No. 5,361,370 - "Single-Instruction Multiple-Data Processor Having Dual-Ported Local Memory Architecture for Simultaneous Data Transmission on Local Memory Ports and Global Port"

Technology Synopsis: The patent addresses performance limitations in Single-Instruction, Multiple-Data (SIMD) processors, which execute the same instruction across multiple data sets in parallel (Compl. Ex. C, ’370 Patent, col. 1:36-42). A key problem is that memory access can stall the processing units ('370 Patent, col. 2:61-68). The invention discloses a dual-ported memory architecture and a block transfer controller that permit data transfers between local and global memory to occur at the same time the processor is executing other instructions, thereby hiding memory latency and improving efficiency ('370 Patent, Abstract).
Asserted Claims: None specified in the complaint.
Accused Features: None specified in the complaint.

U.S. Patent No. 5,644,784 - "Linear List Based DMA Control Structure"

Technology Synopsis: The patent addresses inefficiencies in managing Direct Memory Access (DMA) controllers, which handle data transfers independently of the main CPU. Prior art methods required the CPU to either manage transfers directly or update complex "linked list" data structures in memory, both of which consume valuable CPU cycles (Compl. Ex. D, ’784 Patent, col. 1:12-17). The patented solution is a DMA control structure based on a simple "linear list" of descriptors in memory. The CPU adds new transfer jobs to the end of the list, and the DMA controller reads jobs sequentially from the list, simplifying the control logic and reducing CPU overhead ('784 Patent, Abstract).
Asserted Claims: None specified in the complaint.
Accused Features: None specified in the complaint.

III. The Accused Instrumentality

The complaint does not identify any specific accused products, methods, or services. It broadly seeks a declaration that "[Broadcom's] products do not infringe any valid claim of the Patents In Suit" (Compl. Prayer for Relief ¶a). The basis for the action is an allegation by Intel in a separate proceeding that "charged Broadcom with infringement" (Compl. ¶6). The complaint does not provide sufficient detail for analysis of specific accused functionalities.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not provide specific infringement allegations or claim charts mapping patent claims to accused product features. The action is for a declaratory judgment of non-infringement, based on Intel's charge of infringement in a separate litigation (Compl. ¶6). Therefore, a detailed claim chart summary cannot be constructed from the provided complaint.

Identified Points of Contention: Based on the patent technology and the nature of the parties' businesses, any future infringement analysis may raise the following questions:
- ’887 Patent (VLC Decoding): Does Broadcom’s architecture for decoding variable length codes utilize a two-level table structure with a "major table" for frequent codes and a "minor table" for infrequent ones, as claimed? A central question may be one of architectural equivalence, focusing on whether Broadcom’s implementation, even if functionally similar, is structurally different from the claimed invention.
- ’399 Patent (Pipelined Encoder): What is the precise timing and data dependency of operations within Broadcom's video processing hardware? The analysis may focus on whether key steps like filtering, differencing, and transformation are performed "simultaneously" on "contiguous data values" as specified by the patent claims, or if they are performed in a manner that is temporally or architecturally distinct.

V. Key Claim Terms for Construction

As the complaint does not specify which claims are at issue, the following analysis is based on representative terms from the patents' independent claims that may be central to an infringement dispute.

For the ’887 Patent:
- The Term: "a major table" and "a minor table"
- Context and Importance: The invention is predicated on this two-level table structure. The construction of these terms will determine whether the claims cover only the specific embodiments shown or a broader range of hierarchical table structures designed to optimize cache performance. Practitioners may focus on this term because it defines the structural boundary between the patented invention and other decoding optimization techniques.
- Intrinsic Evidence for Interpretation:
  - Evidence for a Broader Interpretation: The Abstract describes the tables by their function and optimization goal: "The major table has been statistically optimized to contain entries corresponding to frequently used VLCs. The minor table has been optimized for space..." ('887 Patent, Abstract). This functional language could support an interpretation not strictly limited to a particular physical memory layout.
  - Evidence for a Narrower Interpretation: The detailed description of specific embodiments and figures may disclose a particular size, structure, or access method for the tables, which could be argued as limiting the claim scope to what was specifically invented and disclosed.
For the ’399 Patent:
- The Term: "simultaneously"
- Context and Importance: The core inventive concept is the parallel, pipelined nature of the video processing. The definition of "simultaneously" is critical to determining infringement. It raises the question of whether the term requires operations to occur within the same clock cycle or allows for a degree of temporal overlap typical of pipelined systems.
- Intrinsic Evidence for Interpretation:
  - Evidence for a Broader Interpretation: The overall context of a "pipelined architecture" described in the specification may suggest that "simultaneously" should be understood to mean overlapping in a way that increases throughput, not necessarily occurring in the exact same instant.
  - Evidence for a Narrower Interpretation: The Abstract states that a transform device operates on a data value "simultaneously with the performance of a filtering operation upon another one of the three contiguous data values" ('399 Patent, Abstract). This phrasing could support a narrower construction requiring a high degree of temporal overlap between the specified operations.

VI. Other Allegations

The complaint does not contain allegations of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

A central issue will be one of architectural equivalence: The patents-in-suit claim specific hardware and data structure architectures (e.g., two-level decoder tables, pipelined simultaneous processors, linear DMA lists). The case will likely turn on whether Broadcom's products, which perform similar high-level functions, implement them using architectures that are structurally and functionally equivalent to those claimed, or if they employ alternative, non-infringing designs.
A key threshold question will be one of evidentiary proof: As this is a declaratory judgment action filed by the accused infringer, the initial focus will be on discovery. The case's trajectory will depend on what evidence Intel can obtain from Broadcom’s proprietary designs to prove that the accused products meet the specific limitations of patent claims drafted years before those products were likely conceived.