Mentor Graphics Corp v. Quickturn Design Systems Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mentor Graphics Corp (Oregon)
  • Defendant: Quickturn Design Systems, Inc. (Delaware), and Cadence Design Systems, Inc. (Delaware)
  • Plaintiff’s Counsel: Latham & Watkins LLP
• Case Identification: 3:02-cv-01426, N.D. Cal., 03/25/2002
• Venue Allegations: Venue is alleged to be proper based on statutory requirements and the California presence of both Defendants, with Quickturn having principal executive offices in San Jose and Cadence having headquarters in Mountain View.
• Core Dispute: Plaintiff alleges that Defendants’ hardware emulation systems infringe a patent related to Field Programmable Gate Arrays (FPGAs) that incorporate integrated debugging facilities.
• Technical Context: The technology concerns FPGAs, which are configurable semiconductor devices widely used in the electronics industry to prototype, test, and emulate new digital circuit designs before committing to mass production.
• Key Procedural History: The complaint notes the existence of three other pending lawsuits between the parties in the same district, suggesting a broader, ongoing dispute over intellectual property. The complaint also alleges willful infringement based on Defendants’ "previous notice and knowledge of Mentor's patents," which, if proven, could lead to enhanced damages.

Case Timeline

Date	Event
1995-10-13	’489 Patent Priority Date
1998-07-07	’489 Patent Issued
2002-03-25	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,777,489 - "FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED DEBUGGING FACILITIES"

• Patent Identification: U.S. Patent No. 5,777,489, "FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED DEBUGGING FACILITIES," issued July 7, 1998 (’489 Patent). (Compl. ¶5).

The Invention Explained

• Problem Addressed: The patent describes a problem with using conventional FPGAs for circuit emulation: the internal states of logic elements, or "hidden nodes," are not directly observable. Accessing these nodes for debugging traditionally required a "time consuming recompilation" to route the internal signals to external I/O pins, a process which consumes limited I/O resources and can introduce timing distortions. (’489 Patent, col. 1:18-38).
• The Patented Solution: The invention proposes an FPGA with built-in debugging capabilities. This is achieved through "enhanced logic elements (LEs)" that can have their states frozen, read, and modified via an on-chip "context bus." (’489 Patent, Abstract). The architecture also includes a "scan register" to capture and serially output a "snapshot" of the logic states, and "trigger circuitry" to monitor for specific internal events, thereby providing direct, on-chip visibility without recompilation. (’489 Patent, col. 1:44-67; Fig. 1).
• Technical Importance: This integrated approach was designed to significantly accelerate the debugging cycle for complex circuit designs, a critical bottleneck in the development of new electronic systems. (’489 Patent, col. 2:20-29).

Key Claims at a Glance

• The complaint asserts independent claim 14 and dependent claim 15. (Compl. ¶6).
• Independent Claim 14 recites a single integrated circuit comprising:
  • a plurality of logic elements (LEs) for generating a plurality of output signals
  • a scan register coupled to the LEs for serially capturing and outputting a trace record of all signal state values of the LEs in a particular clock cycle of an operating clock
  • trigger circuitry coupled to the LEs for conditionally generating at least one trigger value depending on the signal state values of the LEs

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused products as "hardware emulation systems... identified by the trade name Mercury™." (Compl. ¶6).

Functionality and Market Context

The complaint alleges that the Mercury™ systems are used for hardware emulation and that Defendants are "making, selling, offering to sell, and using" these systems in the United States. (Compl. ¶6). The complaint does not provide further technical detail on the specific features, architecture, or operation of the accused Mercury™ system.

IV. Analysis of Infringement Allegations

The complaint does not provide a detailed, element-by-element mapping of the accused Mercury™ system's features to the limitations of claim 14. It makes a general allegation that the system infringes by "embodying the patented inventions" (Compl. ¶6). Due to the lack of specific factual allegations mapping product features to claim elements, a claim chart summary cannot be constructed from the complaint alone. No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Structural Questions: The infringement analysis will depend on whether the Mercury™ system contains structures that meet the definitions of the key claim elements. A primary question will be whether the accused system contains a "scan register" and "trigger circuitry" as recited in claim 14. The claim further defines the scan register with a specific architecture ("comprising n sets of flip-flops and (n-1) sets of multiplexors"), raising the question of whether the accused product has this precise structure or a legally equivalent one. (’489 Patent, col. 8:12-21).
  • Functional Questions: A point of contention may be whether any debugging or analysis hardware within the Mercury™ system performs the specific functions required by the claims. For example, does it "serially [capture] and [output] a trace record of all signal state values of the LEs in a particular clock cycle," and does it "conditionally [generate] at least one trigger value depending on the signal state values of the LEs"? (’489 Patent, col. 8:10-14, 25-28).

V. Key Claim Terms for Construction

• The Term: "scan register"

• Context and Importance: This term describes a core architectural component of the claimed invention. Claim 14 provides a specific structural definition. The outcome of the infringement analysis may depend on whether this term is construed to be limited to that specific structure or can encompass other hardware configurations that perform a similar function.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party arguing for a broader scope might point to the functional description, where the register's purpose is to "serially [capture] and [output] a trace record" or a "snapshot" of the LEs, suggesting that any hardware performing this function could qualify. (’489 Patent, col. 6:10-15; col. 8:10-14).
  • Evidence for a Narrower Interpretation: A party arguing for a narrower scope will emphasize the detailed structural language within claim 14 itself, which recites "n sets of flip-flops and (n-1) sets of multiplexors serially coupled to each other." (’489 Patent, col. 8:12-21). This argument would be supported by the detailed depiction of this structure in Figure 8 and its accompanying description. (’489 Patent, col. 5:61-col. 6:15).

• The Term: "trigger circuitry"

• Context and Importance: This term is critical for defining the scope of the on-chip monitoring and event-detection capability required by the claim. Infringement will depend on what kind of hardware in the accused product satisfies this limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim language describes the function broadly as "conditionally generating at least one trigger value depending on the signal state values of the LEs." (’489 Patent, col. 8:25-28). This could be argued to cover any form of conditional logic that generates an output based on internal states.
  • Evidence for a Narrower Interpretation: The specification discloses a specific embodiment in Figure 9, which consists of "comparator-register circuits" that compare LE outputs to a stored "signal pattern." (’489 Patent, col. 6:16-24). A party may argue that the term should be limited to this pattern-matching comparator architecture.

VI. Other Allegations

• Indirect Infringement: The prayer for relief seeks an injunction against "contributory infringement or inducement of infringement." (Compl. ¶21). However, the body of the complaint does not contain specific factual allegations detailing acts of inducement (e.g., providing instructions) or contributory infringement (e.g., providing a non-staple component). The infringement count itself only alleges direct infringement. (Compl. ¶6).
• Willful Infringement: The complaint alleges that Defendants' infringement "is and has been willful and deliberate, as Defendants have committed the acts alleged with previous notice and knowledge of Mentor's patents." (Compl. ¶13). This asserts pre-suit knowledge as the basis for willfulness.

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be evidentiary and structural: Given the complaint's lack of technical specifics, a primary question is what evidence Plaintiff will produce to demonstrate that the accused Mercury™ system contains the specific "scan register" and "trigger circuitry" architectures as recited in claim 14 of the ’489 patent, either literally or under the doctrine of equivalents.

2. The case may also turn on a question of claim scope: Will the term "scan register," which is defined in claim 14 with a particular arrangement of flip-flops and multiplexors, be construed to require that specific hardware structure, or can it be interpreted more broadly to cover other architectures that perform the function of serially scanning out internal logic states?