DCT
3:09-cv-05718
Netlist Inc v. Google Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Netlist, Inc. (Delaware)
- Defendant: Google Inc. (Delaware)
- Plaintiff’s Counsel: Pruetz Law Group LLP; Lee Tran & Liang APLC
- Case Identification: 3:09-cv-05718, N.D. Cal., 12/04/2009
- Venue Allegations: Venue is alleged to be proper in the Northern District of California because Defendant Google Inc. has a regular and established place of business in the district, and the alleged acts of infringement occurred there.
- Core Dispute: Plaintiff alleges that Defendant’s use of certain high-density server memory modules infringes a patent related to a memory module decoder that enables a computer system to support more memory than it was designed for.
- Technical Context: The technology addresses limitations in computer memory architecture, where a logic element on a memory module allows it to present a different configuration to the system, thereby increasing memory capacity using lower-cost components.
- Key Procedural History: The complaint does not mention any prior litigation, licensing history, or administrative proceedings related to the patent-in-suit. The patent issued less than three weeks before the complaint was filed.
Case Timeline
| Date | Event |
|---|---|
| 2004-03-05 | ’912 Patent - Earliest Priority Date |
| 2009-11-17 | ’912 Patent - Issue Date |
| 2009-12-04 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,619,912 - "Memory Module Decoder"
- Patent Identification: U.S. Patent No. 7,619,912, "Memory Module Decoder", issued November 17, 2009.
The Invention Explained
- Problem Addressed: The patent addresses the problem that most computer and server systems are designed to support a limited number of memory "ranks" (logical blocks of memory devices), which in turn limits the total memory capacity that can be installed in a given memory slot (’912 Patent, col. 2:38-44).
- The Patented Solution: The invention is a memory module that includes a special "logic element." This logic element intercepts control signals from the computer system that are intended for a small number of ranks (e.g., two) and translates them into a new set of control signals capable of addressing a larger number of physical ranks (e.g., four) actually present on the module (’912 Patent, Abstract; col. 7:1-14). This allows the memory module to "simulate" a configuration that is compatible with the host system, while effectively doubling the memory density.
- Technical Importance: This approach provided an economic incentive to build higher-capacity memory modules using pairs of readily available, lower-cost memory chips instead of waiting for more expensive, next-generation high-density chips to become cost-effective (’912 Patent, col. 5:1-5).
Key Claims at a Glance
- The complaint asserts "one or more claims" without specifying them (Compl. ¶11). The first independent apparatus claim, Claim 1, is representative of the core technology.
- Essential Elements of Independent Claim 1:
- A memory module with a printed circuit board.
- A plurality of double-data-rate (DDR) memory devices arranged in a "first number of ranks."
- A circuit, comprising a "logic element" and a "register," mounted on the printed circuit board.
- The circuit receives "input control signals" from a computer system corresponding to a "second number of ranks," where the second number is less than the first number.
- The circuit generates "output control signals" corresponding to the "first number of ranks."
- A phase-lock loop (PLL) device operatively coupled to the memory devices, logic element, and register.
- The complaint does not explicitly reserve the right to assert dependent claims, but the broad allegation of infringing "one or more claims" preserves this option.
III. The Accused Instrumentality
Product Identification
- "4-Rank Fully Buffered Dual In-Line Memory Modules (4-Rank FBDIMMs)" and "components thereof" (Compl. ¶9, ¶11).
Functionality and Market Context
- The complaint alleges that these are computer memory modules that Google has "sold, offered to sell, made, and/or used" in its server computers (Compl. ¶9).
- The complaint does not provide specific details on the technical operation of the accused 4-Rank FBDIMMs beyond identifying their product category and alleging they "incorporate the Netlist technology claimed in the '912 Patent" (Compl. ¶9).
IV. Analysis of Infringement Allegations
The complaint provides a conclusory allegation of infringement without mapping specific product features to claim elements. The following chart is based on the general allegation that the accused 4-Rank FBDIMMs practice the invention.
’912 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a printed circuit board; | The accused 4-Rank FBDIMMs are memory modules which inherently include a printed circuit board. | ¶9, ¶11 | col. 5:9-11 |
| a plurality of double-data-rate (DDR) memory devices mounted to the printed circuit board, the plurality of DDR memory devices... arranged in a first number of ranks; | The accused products are identified as "4-Rank Fully Buffered Dual In-Line Memory Modules," which comprise DDR memory devices arranged in four physical ranks. | ¶9, ¶11 | col. 6:30-34 |
| a circuit mounted to the printed circuit board, the circuit comprising a logic element and a register, the logic element receiving a set of input control signals from the computer system... corresponding to a second number of... ranks... less than the first number of ranks... | The complaint alleges the accused modules incorporate the patented technology, which implies that a circuit on the module (such as an Advanced Memory Buffer on an FBDIMM) receives control signals from Google's servers corresponding to a number of ranks (e.g., two) that is fewer than the module's physical ranks (e.g., four). | ¶8, ¶9, ¶11 | col. 5:12-20 |
| the circuit generating a set of output control signals in response to the set of input control signals, the set of output control signals corresponding to the first number of... ranks... | The complaint's allegations imply that the circuit on the accused module translates the input control signals to generate output signals that can select among all four physical ranks of the memory devices. | ¶8, ¶9, ¶11 | col. 5:18-20 |
| a phase-lock loop device mounted to the printed circuit board... | The complaint's allegation that the accused modules incorporate the patented technology implies the presence of a phase-lock loop device, a standard component on registered memory modules for clock signal management. | ¶9, ¶11 | col. 5:21-23 |
Identified Points of Contention
Factual Question: The complaint's primary weakness is its lack of factual detail. The central question for discovery will be whether Google's accused "4-Rank FBDIMMs" actually perform the signal translation at the core of the ’912 patent. The infringement case hinges on proving that the modules receive control signals for 'X' ranks from the server but generate internal control signals for 'Y' ranks, where Y > X.
Scope Question: Does the controller on a standard FBDIMM, known as an Advanced Memory Buffer (AMB), meet the claim limitation of "a circuit... comprising a logic element and a register"? The defense may argue that an AMB is a standard component with a different primary purpose and does not meet the specific structural or functional requirements of the claimed circuit.
No probative visual evidence provided in complaint.
V. Key Claim Terms for Construction
The complaint does not provide sufficient detail for a deep analysis, but based on the technology, the following terms will likely be critical.
- The Term: "a circuit... comprising a logic element and a register"
- Context and Importance: This term defines the central translating component of the invention. Whether the on-board controller of the accused FBDIMMs (the AMB) infringes will depend entirely on the construction of this term. Practitioners may focus on this term because its interpretation will determine if a multi-function, standard component like an AMB can satisfy a limitation that the patent figures depict as distinct functional blocks.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states the "logic element" can be a programmable-logic device (PLD), application-specific integrated circuit (ASIC), or other similar devices, and notes that the logic element, register, and PLL could be "portions of a single component" (’912 Patent, col. 6:38-45). This may support construing the term to cover a single integrated chip like an AMB.
- Evidence for a Narrower Interpretation: Figure 1A of the patent depicts the logic element (40) and register (60) as structurally separate blocks. A defendant could argue that this disclosure, along with the use of two different terms ("logic element" and "register"), requires two structurally or at least functionally distinct entities, which may not be present in a highly integrated AMB.
VI. Other Allegations
Indirect Infringement
- The complaint makes conclusory allegations of induced and contributory infringement (Compl. ¶11). It alleges that Google's activities include "contributing to and/or inducing others to make, use, sell, and/or offer for sale such 4-Rank FBDIMMs" and that the components "lack any substantial non-infringing use" (Compl. ¶9, ¶11). No specific facts, such as the provision of instructions or manuals, are alleged to support the knowledge and intent required for these claims.
Willful Infringement
- Willfulness is alleged "on information and belief" (Compl. ¶12). The complaint does not plead any specific facts to support pre-suit knowledge of the patent, such as a notice letter or prior dealings. Given that the patent issued on November 17, 2009, and the complaint was filed on December 4, 2009, any allegation of pre-suit willfulness would require demonstrating that Google became aware of the patent in that very short window.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of claim scope and technical equivalence: Can the claim term "a circuit... comprising a logic element and a register," which the patent illustrates with discrete functional blocks, be construed to read on the integrated Advanced Memory Buffer (AMB) controller found on the accused 4-Rank FBDIMMs? The viability of the infringement case may depend on whether Netlist can prove the AMB performs the specific signal translation function recited in the claims.
- A key evidentiary question will be one of operational function: Independent of claim construction, what evidence will emerge from discovery to demonstrate that Google's servers, when using the accused FBDIMMs, actually operate in the manner claimed—that is, sending control signals for a smaller number of ranks to a module that then internally controls a larger number of physical ranks? The complaint alleges this functionality but provides no supporting facts.