DCT

3:12-cv-01549

Smart Memory Solutions LLC v. Toshiba America Electronic Components Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:12-cv-01549, D. Del., 08/02/2011
  • Venue Allegations: Venue is alleged to be proper because Defendants are subject to personal jurisdiction in the district, are deemed to reside there, regularly transact business in the district, and have allegedly committed acts of infringement in the district.
  • Core Dispute: Plaintiff alleges that Defendants’ microcontroller and microcomputer products containing embedded flash memory infringe a patent related to space-efficient word line driving circuits for semiconductor memory.
  • Technical Context: The technology concerns the design of circuits that select and activate rows of memory cells (word lines) in high-density memory chips, a critical function for balancing operational speed with physical size.
  • Key Procedural History: The complaint notes that the patent-in-suit was assigned to the Plaintiff. No other procedural events, such as prior litigation or administrative proceedings involving the patent, are mentioned.

Case Timeline

Date Event
1995-09-26 '832 Patent Priority Date
1997-05-27 '832 Patent Issue Date
2011-08-02 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,633,832 - "Reduced Area Word Line Driving Circuit for Random Access Memory," Issued May 27, 1997

The Invention Explained

  • Problem Addressed: The patent’s background section describes a challenge in designing high-density random access memories (RAMs). As memory capacities increase, the physical word lines become longer, creating a higher capacitive load that slows down the memory's access speed. Prior art methods for boosting the driving voltage to increase speed often required a large number of components or complex timing signals, which increased the circuit's physical footprint and design complexity, running counter to the goal of miniaturization ('832 Patent, col. 1:24-50).
  • The Patented Solution: The invention claims to solve this problem with a compact word line driver circuit. The design uses a "weak" level shifter transistor that can be "overpowered" by the decoder circuitry ('832 Patent, col. 5:7-18). This allows a standard, logic-level voltage signal to select a word line that is then driven to a higher, boosted voltage (Vpp), achieving high speed without the large device count or complex control signals of prior solutions ('832 Patent, Abstract; Fig. 1).
  • Technical Importance: The patent presents this approach as providing a "boosted word line driver circuit having a reduced layout area" and a "reduced number of active devices," which were important for developing smaller, faster, and more efficient high-density memory chips ('832 Patent, col. 2:34-38).

Key Claims at a Glance

  • The complaint alleges infringement of at least independent claim 1 (Compl. ¶14).
  • The essential elements of independent claim 1 include:
    • A "decoder circuit" that pulls a decode node to a first or second power supply voltage based on decoder and reset signals.
    • A "plurality of word line driver stages," where each stage contains:
    • A "transfer transistor" coupling the decode node to a control node.
    • A "first driver transistor" (e.g., PMOS) to pull the word line up to a "boost voltage."
    • A "second driver transistor" (e.g., NMOS) to pull the word line down to a second supply voltage.
    • A "level shifting transistor" coupled between the boost voltage and the control node, with its gate coupled to the word line.
  • The complaint's focus on "including, without limitation, independent claim 1" suggests the possibility that dependent claims may be asserted later in the litigation (Compl. ¶14).

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused instrumentalities as the embedded flash memory components within specific microcontroller and microcomputer products (Compl. ¶¶15-17). These include:

  • The "Embedded Flash Memory of the Panasonic MN103S26EDC Microcomputer" (Compl. ¶15).
  • The "Embedded Flash Macro of the Toshiba TMP91FY42FG 16-Bit Microcontroller" (Compl. ¶16).
  • The "Embedded Flash Macro of the Fujitsu MB91F248 32-Bit Microcontroller" (Compl. ¶17).

Functionality and Market Context

The complaint describes the accused products generally as "semiconductor products and systems, including microcontroller and microcomputer devices with embedded flash memory" (Compl. ¶¶2-5). It alleges that Defendants are engaged in the business of manufacturing, using, selling, and importing these products (Compl. ¶¶2-5). The complaint does not provide further technical detail regarding the operation of the accused embedded flash memory or its market position.

IV. Analysis of Infringement Allegations

The complaint alleges that the accused devices "embody each element" of at least independent claim 1 of the '832 Patent (Compl. ¶14). However, it does not provide a claim chart or specific factual allegations that map the limitations of the claim to particular components or functions of the accused products. As a result, a detailed claim chart summary cannot be constructed from the complaint. No probative visual evidence provided in complaint.

Identified Points of Contention

  • Scope Questions: The patent is titled and primarily described in the context of "Random Access Memory" (RAM), with specific references to DRAM ('832 Patent, col. 4:32). The accused products contain "embedded flash memory," a form of non-volatile memory (Compl. ¶¶15-17). A central issue may be whether the term "semiconductor memory device" in the claims can be properly construed to cover the architecture of the accused flash memory, or if it is limited by the specification to the volatile RAM context.
  • Technical Questions: A key evidentiary question will be whether the accused products contain the specific transistor-level architecture recited in Claim 1. The analysis will likely focus on whether the accused circuits include a "level shifting transistor" that performs the "overpowering" function described as central to the invention's operation, where it is overcome by the decoder circuit to initiate a word line selection ('832 Patent, col. 5:7-18).

V. Key Claim Terms for Construction

  • The Term: "level shifting transistor"

    • Context and Importance: This element appears to be a point of novelty. Its structure and function, particularly its "weak" nature relative to the decoder circuit, is described as enabling the invention’s space-saving benefits ('832 Patent, col. 5:7-18). Its construction will be critical to the infringement analysis.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A party may argue for a purely structural definition based on the language of claim 1, which defines the transistor by its connections: a "source coupled to the boost voltage, its drain coupled to the control node, and its gate coupled to the word line" ('832 Patent, col. 7:7-10).
      • Evidence for a Narrower Interpretation: A party may argue that the specification imbues the term with a functional requirement, stating that its channel width is "small relative to... the devices making up the decoder circuit" to allow it to be "over-powered" ('832 Patent, col. 5:9-12). This functional context may be used to argue for a narrower definition that includes this relative sizing characteristic.

  • The Term: "decoder circuit"

    • Context and Importance: This is the first major element of the claimed circuit, and its interaction with the transfer and level shifting transistors is fundamental to the claimed operation. Defining the scope of what constitutes a "decoder circuit" will be a foundational step in the infringement analysis.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim functionally defines the circuit as "pulling the control node to the second power supply in response to a plurality of active decoder signals" ('832 Patent, col. 6:48-51). An argument could be made that any structure performing this function meets the limitation.
      • Evidence for a Narrower Interpretation: The patent discloses only one embodiment, which includes "four n-channel transistors (N10-N13) connected in series" ('832 Patent, col. 4:63-65). A party may argue that the term should be construed more narrowly in light of this specific, and only, disclosed implementation.

VI. Other Allegations

Willful Infringement

The complaint alleges that, "upon information and belief, Defendants had knowledge of the '832 Patent at the time they engaged in infringing activities" and that the infringement was "willful and deliberate" (Compl. ¶20). The complaint seeks treble damages for this alleged willful infringement (Compl., p. 6, ¶d). The complaint does not specify the basis for the alleged knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the claims, which the patent specification describes in the context of volatile RAM (e.g., DRAM), be construed to read on the circuitry within the defendants' accused non-volatile embedded flash memory products?
  • A key evidentiary question will be one of structural and functional correspondence: what evidence will be presented to demonstrate that the accused microcontrollers contain the specific, interconnected transistor-level architecture of Claim 1, particularly the "level shifting transistor" that is "overpowered" by the "decoder circuit" in the manner described as inventive in the patent specification?