Synopsys Inc v. Mentor Graphics Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Synopsys, Inc. (Delaware)
  • Defendant: Mentor Graphics Corporation (Oregon)
  • Plaintiff’s Counsel: Kasowitz, Benson, Torres & Friedman LLP; Orrick, Herrington & Sutcliffe LLP
• Case Identification: 3:12-cv-06467, N.D. Cal., 12/21/2012
• Venue Allegations: Plaintiff alleges venue is proper in the Northern District of California because Defendant transacts business, has committed acts of infringement, and maintains research, development, and sales facilities within the district.
• Core Dispute: Plaintiff alleges that Defendant’s Veloce family of hardware emulation products infringes four patents related to electronic design automation (EDA), specifically concerning methods for synthesizing logic circuits from high-level descriptions and for implementing resetable memory.
• Technical Context: Electronic design automation tools are fundamental to the semiconductor industry, enabling engineers to design, verify, and debug the complex integrated circuits that power modern electronics.
• Key Procedural History: The complaint does not mention prior litigation or licensing between the parties. However, U.S. Patent No. 6,836,420, one of the patents-in-suit, was later the subject of an inter partes review (IPR2014-00287), which resulted in the cancellation of several claims, potentially affecting the scope of allegations that can be maintained for that patent.

Case Timeline

Date	Event
1990-12-21	Priority Date for ’488, ’841, and ’318 Patents
1996-06-25	U.S. Patent No. 5,530,841 Issued
1997-10-21	U.S. Patent No. 5,680,318 Issued
1998-05-05	U.S. Patent No. 5,748,488 Issued
2002-03-04	Priority Date for ’420 Patent
2004-12-28	U.S. Patent No. 6,836,420 Issued
2012-12-21	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,748,488 - "Method for Generating a Logic Circuit from a Hardware Independent User Description Using Assignment Conditions"

The Invention Explained

• Problem Addressed: The patent’s background describes a challenge in the automated design of integrated circuits where designers using Hardware Description Languages (HDLs) were still required to have detailed knowledge of specific hardware components, such as flip-flops or latches, rather than being able to describe the circuit's function at a purely operational level (’488 Patent, col. 2:1-11).
• The Patented Solution: The invention provides a method for a logic synthesizer to automatically generate a logic network from a high-level, hardware-independent description provided by a user. This is achieved by converting the user's description into a set of "assignment conditions" that define the circumstances under which signals are produced, and then using these conditions to automatically select and configure the necessary hardware components like latches or three-state drivers (’488 Patent, Abstract; col. 2:22-35).
• Technical Importance: This method increased the level of abstraction in circuit design, enabling designers to focus more on a circuit's intended behavior and less on its specific gate-level implementation, thereby improving productivity (’488 Patent, col. 2:12-21).

Key Claims at a Glance

• The complaint asserts "one or more claims" without specification (Compl. ¶9). Independent claim 1 is a representative method claim.
• Essential elements of Claim 1 include:
  • Converting a hardware independent user description for a logic signal into an assignment condition for an asynchronous load function and an assignment condition for an asynchronous data function.
  • Generating a level sensitive latch when both assignment conditions are non-constant.
  • Wherein the data function assignment condition provides a signal to the data input line of the latch.
  • Wherein the load function assignment condition provides a signal to the gate line of the latch.
  • Wherein the output of the latch is the logic signal.
• The complaint reserves the right to assert additional claims (Compl. ¶9).

U.S. Patent No. 5,530,841 - "Method for Converting a Hardware Independent User Description of a Logic Circuit Into Hardware Components"

The Invention Explained

• Problem Addressed: As with the related ’488 Patent, this invention addresses the inefficiency of prior art HDLs that required designers to possess detailed knowledge of logic elements, which limited the accessibility and speed of automated logic design (’841 Patent, col. 2:1-14).
• The Patented Solution: The patent describes a method implemented in a synthesizer that converts a hardware-independent description into a logic network. The process involves two main stages: a preprocessor that creates a "control flow graph" representing the logic's behavior, and a logic circuit generator that uses this graph to create the physical net list of hardware components (’841 Patent, Abstract; col. 10:40-54).
• Technical Importance: By automating the translation from a behavioral specification to a structural hardware implementation, the invention aimed to make circuit design faster and available to a wider group of engineers with less specialized logic-level expertise (’841 Patent, col. 2:15-24).

Key Claims at a Glance

• The complaint asserts "one or more claims" without specification (Compl. ¶15). Independent claim 1 is a representative method claim and is identical to claim 1 of the ’488 Patent.
• Essential elements of Claim 1 include:
  • Converting a hardware independent user description for a logic signal into assignment conditions for an asynchronous load function and an asynchronous data function.
  • Generating a level sensitive latch when both assignment conditions are non-constant.
  • Wherein the data function assignment condition is a signal on the latch's data input line.
  • Wherein the load function assignment condition is a signal on the latch's gate line.
  • Wherein the latch's output signal is the logic signal.
• The complaint reserves the right to assert additional claims (Compl. ¶15).

U.S. Patent No. 5,680,318 - "Synthesizer for Generating a Logic Network Using a Hardware Independent Description"

Technology Synopsis

This patent, part of the same family as the ’488 and ’841 patents, claims a synthesizer system rather than a method. It addresses the problem of translating a high-level, behavioral circuit description into a concrete hardware implementation by using a preprocessor to create a control flow graph and a logic circuit generator to build the corresponding logic network from that graph, thereby automating a key step in the design process (’318 Patent, Abstract).

Asserted Claims

"one or more claims" (Compl. ¶21).

Accused Features

The complaint alleges that Defendant's Veloce family of products are synthesizers that practice the claimed invention when used to "create, analyze, diagnose, and/or debug integrated circuit designs" (Compl. ¶¶ 21-22).

U.S. Patent No. 6,836,420 - "Method and Apparatus for Resetable Memory and Design Approach for Same"

Technology Synopsis

This patent discloses a method and apparatus for creating a resetable memory system using a primary memory unit that itself lacks a reset function. The invention pairs the primary memory with a smaller, secondary memory that does have a reset capability. This secondary memory stores state bits indicating whether a corresponding cell in the primary memory has been written to since the last reset, and a multiplexer uses these state bits to output either the actual data from the primary memory or a default reset value (’420 Patent, Abstract).

Asserted Claims

"one or more claims" (Compl. ¶27).

Accused Features

The complaint alleges that Defendant's Veloce family of products practices the claimed inventions for implementing resetable memory in the course of emulating customer circuit designs (Compl. ¶¶ 27-28).

III. The Accused Instrumentality

Product Identification

The "Veloce family of emulation products and their related services" (Compl. ¶9).

Functionality and Market Context

The complaint describes the accused products as Electronic Design Automation (EDA) tools used by engineers to "create, analyze, diagnose, and/or debug integrated circuit designs" (Compl. ¶10). These are hardware emulation systems, which allow designers to verify the functionality of a chip design at high speed before fabrication. Synopsys alleges that in the course of emulating a user's design, these products necessarily perform the patented methods of logic synthesis and implement the patented memory structures (Compl. ¶¶ 9, 15, 21, 27). Both Plaintiff and Defendant are described as major providers in the EDA market (Compl. ¶¶ 1-2). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not provide sufficient detail for a claim-chart analysis. The infringement allegations are conclusory and do not map specific features of the Veloce products to the elements of any asserted claim. The narrative infringement theory suggests that by their nature and intended use, the accused emulation products must perform the patented synthesis methods and implement the patented memory architectures (Compl. ¶¶ 10, 16, 22, 28).

• Identified Points of Contention:
  • Technical Questions: A primary factual dispute may be whether the Veloce emulation platform's internal operations constitute "generating a logic circuit from a hardware independent user description," as claimed in the ’488 and ’841 patents. The process of mapping a design onto an emulator may differ fundamentally from the synthesis process described in the patents, which involves creating a new net list of standard logic elements. The complaint provides no technical evidence to support its assertion that these processes are equivalent.
  • Scope Questions: A legal question may arise regarding whether the input files used by the Veloce system (e.g., RTL-level Verilog or VHDL) qualify as a "hardware independent user description" in the context of the patents. A defendant could argue that such descriptions are not "independent" in the manner contemplated by the inventors in the early 1990s, as they often imply specific hardware structures like registers and buses.

V. Key Claim Terms for Construction

"hardware independent user description"

(’488 Patent, Claim 1; ’841 Patent, Claim 1)

Context and Importance

This term is foundational to the ’488 and ’841 patents, defining the starting point for the claimed synthesis method. The case's outcome may depend on whether the design files processed by the Veloce system fall within this definition. Practitioners may focus on this term because the nature of "hardware independent" design has evolved significantly since the patents' priority date.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The specification states that such a description "specifies only signals and the circumstances under which the signals are produced" and that it allows for use by "designers with limited logic knowledge" (’488 Patent, col. 2:24-32). This could support an interpretation covering any high-level behavioral description.
• Evidence for a Narrower Interpretation: The specification contrasts the invention with prior art HDL that "still required detailed logic knowledge for most practical circuits" (’488 Patent, col. 2:8-10). A defendant may argue that modern RTL descriptions, which are inputs to emulation systems, require a degree of structural and hardware awareness that places them outside the scope of what the patent considers "independent."

"generating a level sensitive latch"

(’488 Patent, Claim 1; ’841 Patent, Claim 1)

Context and Importance

This term recites a specific hardware outcome of the claimed method. Infringement requires proof that the accused products actually perform this step under the specified conditions. A defendant may argue its tools use different optimization algorithms or target different hardware primitives that do not involve "generating a level sensitive latch" as claimed.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The specification provides numerous examples of generating various hardware elements, framing it as an automatic process. The patent states the synthesizer "independently determines the logic elements required" based on operational characteristics (’841 Patent, col. 10:11-15).
• Evidence for a Narrower Interpretation: The claim links this "generating" step to a specific trigger: "when both said assignment condition AL(Q) and said assignment condition AD(Q) are non-constant." This creates a precise, multi-part test. A defendant could argue its process is not governed by this specific logic, thus avoiding infringement.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement. The inducement theory is based on Mentor allegedly "instructing said customers to use its products in a manner that directly infringes" the patents, presumably through user manuals and product documentation (Compl. ¶10). The contributory infringement theory alleges the Veloce products are a material component not suitable for substantial non-infringing use (Compl. ¶11).
• Willful Infringement: The complaint alleges willful infringement based on Defendant’s knowledge of the patents "at least as of the date of this Complaint" (Compl. ¶¶ 10, 16, 22, 28). This suggests the claim is based on alleged post-suit continuation of infringement rather than pre-suit knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of technical equivalence: Can Synopsys present sufficient evidence to prove that the process of configuring a design for a hardware emulator, as performed by the Veloce products, is the same as the claimed methods of "synthesizing" a logic circuit from a hardware-independent description?
• The case will also turn on a question of definitional scope: Will the term "hardware independent user description," rooted in the EDA landscape of the early 1990s, be construed broadly enough to cover the sophisticated RTL design files used as inputs to modern emulation systems?
• For the ’420 patent, a critical question will be validity: Given that an inter partes review resulted in the cancellation of numerous claims, the viability of the remaining asserted claims will be a primary focus of the dispute.