DCT

3:20-cv-04151

Synopsys Inc v. Siemens In

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:20-cv-04151, N.D. Cal., 04/26/2023
  • Venue Allegations: Venue is alleged to be proper based on the original defendant, Avatar Integrated Systems, Inc., having had a regular and established place of business in the judicial district, and on Siemens having submitted to venue by substituting itself for Avatar.
  • Core Dispute: Plaintiff alleges that Defendant’s Aprisa software, an electronic design automation (EDA) tool, infringes three patents related to methods for physical synthesis, multi-threaded routing, and fixing design violations in integrated circuit design.
  • Technical Context: The lawsuit concerns the highly specialized field of EDA software, which is essential for designing complex modern integrated circuits (ICs), also known as semiconductor chips.
  • Key Procedural History: The original complaint was filed against Avatar Integrated Systems, Inc. on June 23, 2020. Avatar had previously acquired the accused Aprisa product from ATopTech, Inc. in an April 2017 bankruptcy proceeding. Plaintiff alleges providing pre-suit notice of the patents-in-suit to Avatar via a letter dated June 16, 2020. Avatar subsequently merged into Siemens, which was substituted as the defendant in this action on December 21, 2020.

**Case Timeline**

Date Event
2008-06-05 Earliest Priority Date ('’614 Patent)
2008-06-24 Earliest Priority Date ('’915 Patent)
2010-11-18 Earliest Priority Date ('’655 Patent)
2010-12-14 '915 Patent Issued
2012-07-31 '614 Patent Issued
2013-03-26 '655 Patent Issued
2017-04-18 Avatar acquires Aprisa product from ATopTech
2020-05-25 Plaintiff sends letter to Avatar regarding IP concerns
2020-06-16 Plaintiff sends letter to Avatar alleging infringement of patents-in-suit
2020-06-23 Original Complaint filed against Avatar
2020-12-02 Avatar files statement disclosing merger into Siemens
2020-12-21 Siemens substituted as Defendant
2023-04-26 Amended and Supplemental Complaint filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,853,915 - *“Interconnect-driven physical synthesis using persistent virtual routing,”*

The Invention Explained

  • Problem Addressed: In modern integrated circuit design, accurately predicting the signal delay caused by the wires ("interconnects") before they are physically routed is a critical challenge. Inaccurate pre-routing estimates can mislead circuit optimization tools, causing them to focus on non-critical parts of a design while leaving truly critical paths un-optimized, leading to poor chip performance and difficult design convergence (Compl. ¶20; ’915 Patent, col. 1:11-32).
  • The Patented Solution: The invention proposes a "persistence-driven" optimization method. The process identifies and ranks the most unpredictable and timing-sensitive signal paths ("nets") in a design. A small percentage of these top-ranked nets are then physically routed using a global router. The actual, accurate delay and parasitic data from these routes is fed back ("back-annotated") into a timing model. Circuit synthesis and optimization are then performed using this highly accurate, real-world data. The routes for these "persistent nets" are preserved through subsequent design stages to ensure that the optimization remains valid (’915 Patent, Abstract; Fig. 4).
  • Technical Importance: This approach aimed to bridge the gap between logical design optimization and physical reality, improving the correlation between pre-route timing estimates and post-route performance, a crucial step for achieving timing closure in complex designs (’915 Patent, col. 2:48-54).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶25).
  • Essential elements of Claim 1 include:
    • A method of performing physical synthesis using persistence-driven optimization.
    • Ranking nets in a design based on unpredictability and expected quality-of-result impact.
    • Selecting a first predetermined top percentage of the ranked nets as first persistent nets.
    • Performing timing-driven global routing on the first persistent nets.
    • Back-annotating a timing graph with actual delays and parasitics from the routing.
    • Running synthesis for the nets using the actual delays and parasitics, wherein synthesis maintains and updates routing for the first persistent nets.
    • The claim continues with steps for a second iteration (re-ranking, selecting a second set of persistent nets, etc.) and concludes with outputting a final layout.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 8,234,614 - *“Multi-threaded global routing,”*

The Invention Explained

  • Problem Addressed: The global routing phase of IC design, which determines the general paths for millions of wires, is computationally intensive and a major bottleneck. Applying parallel processing techniques like multi-threading is difficult because different nets may compete for the same physical routing space, creating interdependencies that are hard to manage in a concurrent environment (’614 Patent, col. 1:10-52).
  • The Patented Solution: The patent describes a method to parallelize the global routing process. It first ranks the global nets based on priority (e.g., timing-critical nets first). It then selects a subset of these nets (a "window") and routes them concurrently using multiple threads, with each thread routing its assigned net "in isolation" from the others in that same window. After the first subset is routed, a second subset is identified and routed, but this time "in respect of" the routes already laid down by the first subset, thereby managing dependencies between routing stages while enabling parallelism within each stage (’614 Patent, Abstract; Fig. 1).
  • Technical Importance: This method allows for the use of multi-core processors to significantly speed up the time-consuming global routing stage, a key factor in reducing overall chip design cycle time (’614 Patent, col. 1:14-20).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶35).
  • Essential elements of Claim 1 include:
    • A method of routing a semiconductor chip's global nets.
    • Ranking the global nets, with the ranking including at least one of: ranking power/ground nets over clock signal nets; ranking power/ground nets over timing/slew critical nets; ranking clock signal nets over timing/slew critical nets; or ranking shorter/lower fan-out nets over longer/higher fan-out nets.
    • Identifying a subset of the global nets.
    • Routing said subset of global nets using multiple threads, where each net within the subset is routed by one thread in isolation of the subset's other global nets.
    • Identifying a second subset of the global nets.
    • Routing the second subset using multiple threads... in respect of the routes of the first subset.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 8,407,655 - *“Fixing design requirement violations in multiple multi-corner multi-mode scenarios,”*

  • Technology Synopsis: The patent addresses the challenge of fixing design violations (e.g., timing errors) in an IC, where a fix for one operating condition (a "scenario," such as high temperature and low voltage) might create a new problem in another. The invention proposes using a compact "multi-scenario engineering change order (ECO) database" that stores a subset of key parameter values from all relevant scenarios. This allows an EDA tool to efficiently estimate the cross-scenario impact of a proposed design change (an ECO) without needing to load and analyze each full, memory-intensive scenario file individually (’655 Patent, Abstract; col. 2:5-14).
  • Asserted Claims: The complaint asserts independent claim 6 (Compl. ¶45).
  • Accused Features: The complaint alleges that Aprisa’s "Multi-corner Multi-mode Analysis" functionality infringes. Specifically, it points to Aprisa's use of a "hierarchical database," "common 'analysis engines'," and its ability to analyze an "unlimited number of scenarios" to fix design violations as mapping to the claimed method (Compl. ¶45, claim chart).

III. The Accused Instrumentality

Product Identification

  • The Siemens Aprisa software product (Compl. ¶24).

Functionality and Market Context

  • Aprisa is described as a "complete full-functioned block-level place and route (P&R) system" used for designing integrated circuits (Compl. ¶25). Its functions include placement, clock tree synthesis, routing, optimization, and embedded analysis (Compl. ¶25). The complaint highlights its "Detailed-Route-Centric P&R Architecture" and a "Route Service Engine (RSE)" that provides routing information to other engines throughout the design flow (Compl. ¶¶7, 8). The software is also alleged to perform "Multi-corner Multi-mode Analysis" to handle design verification across different operating scenarios (Compl. ¶45).
  • The complaint positions Aprisa as a competitor to Plaintiff's own EDA products, such as IC Compiler and PrimeTime (Compl. ¶¶2, 4). The product was acquired by Siemens through its merger with Avatar, which had previously acquired the product assets from ATopTech in a 2017 bankruptcy proceeding (Compl. ¶¶5, 8).

IV. Analysis of Infringement Allegations

’915 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of performing physical synthesis using persistence-driven optimization... Siemens' Aprisa product performs a method of physical synthesis using persistence-driven optimization, described as an iterative process of fixing timing and routing. ¶25 col. 3:41-47
ranking nets in a design based on unpredictability and expected quality-of-result impact; Aprisa's placement and optimization engines iterate between various critical factors, and its global routing engine prioritizes "high-impact nets" or "critical nets." ¶25 col. 4:4-6
selecting a first predetermined top percentage of the ranked nets as first persistent nets; Aprisa is alleged on information and belief to prioritize "critical nets" and select a top percentage of ranked nets based on factors like timing uncertainty. ¶25 col. 4:7-14
performing timing-driven global routing on the first persistent nets; Aprisa's "fast global route engine" performs timing-driven routing, including "Iterative fixing of timing and routing to achieve timing closure." ¶25 col. 4:15-19
back-annotating a timing graph with actual delays and parasitics determined by performing the timing-driven global routing on the first persistent nets; Aprisa's "Unified Data Model (UDM)" is alleged to be a single database for placement, optimization, and routing, making design information like actual delays and parasitics available to any engine. ¶25 col. 4:25-32
running synthesis for the nets in the design using the actual delays and the parasitics for the first persistent nets, wherein the synthesis maintains and updates routing for the first persistent nets; Aprisa is alleged to use actual delays and parasitics to run synthesis, which "happens through out the flow, during placement, CTS, and both global route and detailed routing." ¶25 col. 4:20-24
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the term "persistence-driven optimization" is limited to the specific multi-iteration sequence described in the claim, or if it can be construed more broadly to cover general iterative optimization. The complaint's evidence relies heavily on marketing descriptions from Siemens's and Avatar's websites. A court will need to determine if the actual operation of the Aprisa software, as revealed in discovery, maps to the specific claim elements.
    • Technical Questions: What evidence does the complaint provide that Aprisa's "ranking" of "critical nets" is based on the claimed factors of "unpredictability" and "expected quality-of-result impact"? The defense may argue its ranking is based on different or more conventional metrics. Furthermore, does the Aprisa "Unified Data Model" perform the specific function of "back-annotating a timing graph" as required by the claim, or does it represent a more general data-sharing architecture?

’614 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of routing a semiconductor chip's global nets... Siemens' Aprisa product performs a method of routing global nets, for example, its "fast global route engine can route millions of nets in minutes." ¶35 col. 1:45-52
ranking said semiconductor chip's global nets, wherein said ranking includes at least one of the following: ranking power/ground nets over clock signal nets... Aprisa allegedly ranks global nets by prioritizing power/ground nets, clock signal nets, and timing/slew critical nets using features like "Parametric multit-headed [sic] routing for power/ground grid creation." ¶35 col. 2:20-30
identifying a subset of said global nets; In order to "route millions of nets," it is alleged that Aprisa must identify a subset of global nets to begin the routing process. ¶35 col. 2:5-10
routing said subset of global nets using multiple threads, each of said global nets within said subset routed by one of said threads in isolation of said subset's other global nets; Aprisa is alleged to use "state-of-the-art multi-threading and distributed processing technology," and the complaint asserts that the application of multi-threading means global nets are routed independently. ¶35 col. 2:37-40
identifying a second subset of said global nets; On information and belief, Aprisa's routing features are alleged to identify a second subset of nets with which to continue processing after a first subset is routed. ¶35 col. 2:41-43
routing said second subset of global nets using said multiple threads... but in respect of the routes of said subset of global nets. On information and belief, Aprisa's "router-centric solution which considers route effects" is alleged to mean that the second subset is routed in respect of the routes of the first subset. ¶35 col. 2:41-46

No probative visual evidence provided in complaint.

  • Identified Points of Contention:
    • Scope Questions: The interpretation of the term "in isolation" will be critical. The complaint alleges that the use of "multi-threading" inherently means the nets are routed "independently" and thus in isolation. The defense may argue that "in isolation" requires a higher degree of separation than what occurs in a typical multi-threaded router that may still rely on shared data like a congestion map, and that the term is not synonymous with "concurrently."
    • Technical Questions: Does the Aprisa software perform the distinctly sequential process of identifying a first subset, routing it, and then identifying a second subset to route "in respect of" the first? The complaint's allegations for these specific steps rely on "information and belief" and logical inference rather than direct statements from the accused product's documentation.

V. Key Claim Terms for Construction

  • Term (’915 Patent): "persistence-driven optimization"

    • Context and Importance: This term appears in the preamble of the asserted claim and describes the overall method. Its construction will determine whether Aprisa's iterative optimization loop falls within the claim's scope, or if the claim is limited to a more specific, narrowly defined process.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The Summary of the Invention describes the concept more generally, stating that "persistent virtual routing can advantageously guarantee net routes for the most sensitive nets" and that "persistence can achieve accuracy and predictability" (’915 Patent, col. 3:19-26). This could support a construction covering a range of iterative, feedback-based optimization methods.
      • Evidence for a Narrower Interpretation: The detailed description and Figure 4 lay out a very specific, multi-step flowchart for the process, including distinct phases of ranking, selecting, routing, back-annotating, synthesizing, and then re-ranking (’915 Patent, Fig. 4; col. 7:5-67). This may support a narrower construction limited to methods that follow this particular sequence.

  • Term (’614 Patent): "in isolation"

    • Context and Importance: This term defines the nature of the concurrent routing required by the claim. The infringement question for the first routing step hinges on whether Aprisa's multi-threaded routing operates "in isolation."
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification states, "individual nets within a window are routed in isolation from one another. That is, within a window of nets that are concurrently routed, a net's routing is undertaken without reference to the routing of other nets within the same window" (’614 Patent, col. 2:32-37). This language could support an interpretation where "isolation" means a lack of real-time, direct inter-thread communication about routing decisions for nets within the same processing batch.
      • Evidence for a Narrower Interpretation: The patent later discusses detecting "conflicts" if two nets "impermissibly occupy the same chip surface region," and then strategically eliminating one of the routes (’614 Patent, col. 2:37-43). This post-routing conflict check implies that while the initial routing is concurrent, it is not entirely ignorant of shared resource constraints, potentially supporting a narrower definition of "isolation" that the accused product may not meet.

VI. Other Allegations

  • Indirect Infringement: For all three patents, the complaint alleges induced infringement (§ 271(b)) and contributory infringement (§ 271(c)). The allegations are based on Siemens providing the Aprisa software along with product literature, webpages, and resource libraries that allegedly instruct and encourage customers to use the software in an infringing manner (Compl. ¶¶26-27, 36-37, 46-47).
  • Willful Infringement: Willfulness is alleged for all three patents. The complaint asserts that Siemens had actual knowledge of the patents, or was willfully blind to their existence, no later than upon Avatar’s receipt of a June 16, 2020 letter from Synopsys’s counsel that specifically identified the patents-in-suit (Compl. ¶¶29, 39, 49).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case may depend on the answers to two central questions:

  • A core issue will be one of evidentiary mapping: can Plaintiff demonstrate through technical evidence, such as source code analysis and expert testimony, that the high-level marketing language used to describe the Aprisa software corresponds to the specific, multi-step methods recited in the asserted patent claims, or will Defendant show a fundamental mismatch in technical operation?
  • A key legal question will be one of definitional scope: for the multi-threading patent ('614), can the term "in isolation" be construed to cover concurrent routing where threads may rely on shared, static data like a congestion map, or does it require a stricter form of computational independence that the accused product does not possess?