DCT

3:20-cv-04151

Synopsys Inc v. Siemens In

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:20-cv-04151, N.D. Cal., 07/06/2020
  • Venue Allegations: Venue is alleged to be proper as both parties are Delaware corporations with their principal places of business in Santa Clara County, California, within the judicial district.
  • Core Dispute: Plaintiff alleges that Defendant’s Electronic Design Automation (EDA) software products infringe six patents related to methods for designing, analyzing, and optimizing complex integrated circuits.
  • Technical Context: The lawsuit concerns EDA software, which is a foundational technology used by semiconductor companies to design and verify the complex microchips that power modern electronics.
  • Key Procedural History: The complaint alleges that Defendant, Avatar, acquired the accused Aprisa and Apogee products from ATopTech, Inc. following a 2017 bankruptcy proceeding. Plaintiff also alleges that it provided Defendant with notice of the asserted patents in letters dated May and June 2020, prior to filing the complaint.

Case Timeline

Date Event
2001-06-08 ’863 Patent Priority Date
2006-09-05 ’863 Patent Issue Date
2007-01-10 ’567 Patent Priority Date
2008-06-05 ’614 Patent Priority Date
2008-06-24 ’915 Patent Priority Date
2009-06-09 ’567 Patent Issue Date
2010-08-25 ’640 Patent Priority Date
2010-11-18 ’655 Patent Priority Date
2010-12-14 ’915 Patent Issue Date
2012-07-31 ’614 Patent Issue Date
2013-03-26 ’640 Patent Issue Date
2013-03-26 ’655 Patent Issue Date
2017-04-18 Avatar acquires assets from ATopTech
2020-05-25 Plaintiff sends letter to Defendant regarding alleged IP misuse
2020-06-16 Plaintiff sends letter to Defendant identifying asserted patents
2020-07-06 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,407,640 - "Sensitivity-Based Complex Statistical Modeling for Random On-Chip Variation"

  • Issued: March 26, 2013

The Invention Explained

  • Problem Addressed: As semiconductor manufacturing processes shrink, random on-chip variations (OCV) in transistor performance become a major source of timing uncertainty. Traditional analysis methods that use a single worst-case "derating" value to account for OCV are often overly pessimistic, while full statistical static timing analysis (SSTA) is computationally expensive and difficult to adopt due to its complex data requirements (’640 Patent, col. 1:23-55).
  • The Patented Solution: The patent proposes a method called Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV) that models local random variations using statistical distributions. It introduces a "complex variation concept" which allows for the accurate calculation of timing when circuit paths share common elements, a process known as common-path pessimism removal (CPPR), thereby reducing pessimism without the full cost of SSTA (’640 Patent, Abstract; col. 2:15-21). The solution provides statistical min/max operations for combining the timing of converging circuit paths in a way that guarantees accuracy at a specified statistical corner (e.g., "N-sigma") (’640 Patent, col. 2:22-32).
  • Technical Importance: This approach provided a practical middle ground between overly pessimistic derating methods and cost-prohibitive full statistical analysis, enabling more accurate and efficient timing sign-off for complex chip designs (’640 Patent, col. 2:32-39).

Key Claims at a Glance

The complaint asserts independent claim 1 and reserves the right to assert others (Compl. ¶26).

  • A computer-implemented method of statistical static timing analysis (SSTA) comprising:
  • Receiving information describing a circuit with at least two paths converging at an output node.
  • Each path is associated with a parametric delay represented by a nominal delay value and a standard deviation value.
  • Performing SSTA based on an on-chip variation (OCV) model.
  • The SSTA comprises determining a parametric delay at the output node based on a statistical maximum of the parametric delays through the converging paths.
  • This statistical maximum calculation preserves N sigma corner delay values.
  • The calculation involves determining a nominal delay value and a standard deviation value for the output node's parametric delay.
  • Storing the resulting nominal delay and standard deviation values.

U.S. Patent No. 7,103,863 - "Representing the design of a sub-module in a hierarchical integrated circuit design & analysis system"

  • Issued: September 5, 2006

The Invention Explained

  • Problem Addressed: Modern integrated circuits are designed hierarchically, breaking a large design into smaller, manageable "blocks." However, verifying the timing and electrical integrity often requires analyzing how these blocks interact, a "cross-boundary analysis" that can defeat the purpose of hierarchy by requiring large amounts of data from adjacent blocks, increasing memory usage and runtime (’863 Patent, col. 3:41-52).
  • The Patented Solution: The patent describes creating a "block abstraction," which is a reduced model of a design block. This abstraction is not a simplified mathematical model but a carefully selected "sub-set of the design data itself" (’863 Patent, col. 7:14-17). It retains only the essential logical cells and physical interconnect information necessary to accurately model the block's behavior at its boundaries, while discarding all internal, non-essential data. This allows for accurate cross-boundary analysis without loading the entire block design, preserving the efficiency of the hierarchical flow (’863 Patent, Abstract; col. 4:5-14).
  • Technical Importance: This method enabled more efficient verification of large, hierarchical IC designs by creating lightweight, accurate models of sub-circuits, making it practical to analyze the interfaces between hundreds or thousands of blocks in a complex system-on-chip.

Key Claims at a Glance

The complaint asserts independent claim 1 and reserves the right to assert others (Compl. ¶36).

  • A method for producing a design of a hierarchically decomposed integrated circuit, comprising:
  • Processing at least one block to create an abstraction that includes physical interconnect information.
  • This processing includes retaining only a sub-set of the physical interconnect information that influences the physical and electrical behavior of the parent block.
  • The processing also includes retaining only a sub-set of the cells that influence the logical behavior of the parent block.
  • Utilizing the created abstraction in another development phase performed on the parent block.

U.S. Patent No. 7,546,567 - "Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip"

  • Issued: June 9, 2009 (Compl. ¶20)
  • Technology Synopsis: The patent addresses the problem of on-chip variation (OCV) causing clock skew, which degrades timing performance. The disclosed solution is a method for clock tree synthesis that clusters registers based not only on physical location but also on their "timing criticality." By grouping registers that have tight timing constraints between them, the method facilitates the use of commonly-shared clock paths, which makes their relative timing less susceptible to OCV and reduces skew (’567 Patent, Abstract; col. 2:11-25).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶46).
  • Accused Features: The complaint alleges that Avatar's Aprisa software, specifically its "Clock Tree Synthesis (CTS) and Optimization" features such as "Cluster-based clock trees," "Skewgroup-based CTS," and "Slack-driven CTS," infringe the ’567 Patent (Compl. ¶46, pp. 22-23).

U.S. Patent No. 7,853,915 - "Interconnect-driven physical synthesis using persistent virtual routing"

  • Issued: December 14, 2010 (Compl. ¶21)
  • Technology Synopsis: The patent addresses the inaccuracy of interconnect delay predictions made before the final routing stage of chip design, which can mislead the optimization process. The invention is a "persistence-driven optimization" method where a small number of the most timing-critical and unpredictable signal paths ("nets") are identified, routed early, and their routing paths are made "persistent." This provides the optimization engines with accurate, real-world delay data for the most important nets, leading to better optimization outcomes (’915 Patent, Abstract; col. 3:15-32).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶56).
  • Accused Features: The complaint alleges infringement by Aprisa's "persistence-driven optimization" features, including its "Detailed-Route-Centric" architecture and its "Route Service Engine (RSE)," which are alleged to rank and prioritize nets for routing early in the design flow (Compl. ¶56, pp. 26-29).

U.S. Patent No. 8,234,614 - "Multi-threaded global routing"

  • Issued: July 31, 2012 (Compl. ¶22)
  • Technology Synopsis: This patent aims to speed up the computationally intensive global routing phase of chip design by using parallel processing. The method involves routing a first subset of global nets using multiple threads, where each net is routed in isolation of others in the same subset. A second subset is then routed, also with multiple threads, but in respect of the routes already laid down by the first subset. This allows for concurrent routing while managing the potential for conflicts between threads working on the same physical space (’614 Patent, Abstract; col. 2:5-18).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶66).
  • Accused Features: The complaint accuses Aprisa's "multi-threading and distributed processing technology," which is advertised as being used for its global routing engine, of infringing the ’614 Patent (Compl. ¶66, p. 38; Compl. ¶75, p. 43).

U.S. Patent No. 8,407,655 - "Fixing design requirement violations in multiple multi-corner multi-mode scenarios"

  • Issued: March 26, 2013 (Compl. ¶23)
  • Technology Synopsis: The patent addresses the challenge of fixing design violations across a vast number of different "scenarios" (combinations of manufacturing process corners, operating conditions, and functional modes). The invention proposes a system that uses a "multi-scenario ECO database," which stores a targeted subset of critical parameter values from all scenarios. This allows an engineering change order (ECO) to be evaluated against all scenarios simultaneously by consulting the compact database, rather than sequentially loading each massive full-scenario design file (’655 Patent, Abstract; col. 2:4-11).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶76).
  • Accused Features: Aprisa's "Multi-corner Multi-mode Analysis" and its use of a "Unified Data Model" and "scenario image" to handle an "unlimited number of scenarios" are accused of infringing the ’655 Patent (Compl. ¶76, pp. 43-45).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are the Avatar Aprisa and Avatar Apogee software products (Compl. ¶35).

Functionality and Market Context

  • Aprisa is described as a "complete full-functioned block-level place and route (P&R) system" used for integrated circuit design (Compl. ¶16). Its functions include placement, clock tree synthesis, routing, optimization, and static timing analysis (Compl. ¶16, ¶26). The complaint includes a diagram illustrating Aprisa's "Unified Hierarchical Runtime Data Model" architecture (Compl. ¶26, p. 14).
  • Apogee is a "top down floor planning and chip assembly tool" that complements Aprisa and shares its core engines (Compl. ¶36, p. 17). The complaint alleges these products directly compete with Plaintiff's own EDA tools (Compl. ¶3).

IV. Analysis of Infringement Allegations

8,407,640 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
[A method...] comprising: receiving, by a computer, information describing a circuit, the information comprising: a first input node, a second input node, and an output node, such that there is a first path...and a second path...converging at the output node, The Aprisa tool operates on a computer and receives circuit design information in standard formats (e.g., Verilog), which describe circuits containing converging paths. ¶26 col. 5:15-20
each path associated with a parametric delay represented as a nominal delay value and a standard deviation value... Aprisa receives Liberty Variation Format (LVF) files that represent cell delays using mean (nominal) and standard deviation values, which it uses to associate with circuit paths. ¶26 col. 3:36-40
performing statistical timing analysis (SSTA) based on on-chip variation (OCV) model, the SSTA comprising, determining a parametric delay at the output node based on a statistical maximum of parametric delay through the first path and parametric delay through the second path, wherein the statistical maximum preserves N sigma corner delay values... Aprisa performs statistical timing analysis using an OCV model. It allegedly uses a statistical maximum operator that preserves N-sigma corner delay values to avoid pessimism and achieve correlation with sign-off tools. The complaint cites histograms from a 2019 article showing tight correlation between Aprisa's timing and "signoff STA" (Compl. ¶26, p. 12). ¶26 col. 2:22-29
...determining a nominal delay value of the parametric delay at the output node based on a maximum of: nominal delay value... through the first path, and nominal delay... through the second path; and Aprisa allegedly determines the nominal delay at the output as the maximum of the nominal delays of the two converging paths. ¶26 col. 7:48-50
...determining a standard deviation value of the parametric delay at the output node... Aprisa allegedly determines the standard deviation of the output delay based on the larger N-sigma delay of the two paths to preserve the corner delay value. ¶26 col. 7:51-56
storing the nominal delay and the standard deviation value of the parametric delay for the output node. Aprisa stores the calculated nominal and standard deviation values for the output node in its "unified database" for use in subsequent analysis. The complaint includes a diagram showing the "Avatar Unified Database" as central to the tool's architecture (Compl. ¶26, p. 14). ¶26 col. 5:35-39

Identified Points of Contention

  • Scope Questions: A central question may be whether Aprisa's "statistical OCV (SOCV) methodology" (Compl. ¶26) performs the specific calculation required by the claim limitation "wherein the statistical maximum preserves N sigma corner delay values." The defense may argue that achieving a similar result (correlation with sign-off tools) does not mean it uses the patented method.
  • Technical Questions: What evidence does the complaint provide that Aprisa's algorithm for combining standard deviations is the same as, or equivalent to, the method claimed? The complaint's infringement theory relies heavily on marketing materials, user guides, and analysis of a third-party patent ('700 Patent) assigned to Avatar, rather than direct evidence of the accused product's internal operations.

7,103,863 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method used in producing a design of an integrated circuit said circuit design having...a representation that is hierarchically decomposed into a top-level and a plurality of blocks... Avatar's Aprisa and Apogee products produce IC designs and support hierarchical design, including top-level and block-level representations. ¶36 col. 1:36-46
...said method comprising: processing at least one of said blocks such that an abstraction is created that includes physical interconnect information... Aprisa processes design blocks to create an abstraction. Its "In-Hierarchy Optimization" and "Interconnect Centric 'Precision Optimization'" features are alleged to use physical interconnect information, such as parasitic extraction data. ¶36 col. 2:57-65
...wherein said processing includes: retaining only a sub-set of all of said physical interconnect information which influences physical and electrical behavior of said parent block; and Aprisa's "on-the-fly timing and physical abstraction" feature is alleged to retain only a subset of physical and electrical information by "eliminat[ing] creating of extra files and models for blocks." ¶36 col. 7:14-17
retaining only a sub-set of cells which influences a logical behavior of said parent block; and Aprisa's abstraction feature is alleged to retain only a subset of cells influencing logical behavior, as evidenced by marketing claims that it reduces run time and memory by eliminating extra files and models. ¶36 col. 7:5-14
utilizing said abstraction in another development phase performed on said parent block. The complaint alleges Aprisa uses the created abstraction during subsequent phases like "top-level timing closure," "virtual top level timing optimization," and placement and routing optimization performed on the parent block. ¶36 col. 4:15-24

Identified Points of Contention

  • Scope Questions: The dispute may center on the term "retaining only a sub-set." Defendant may argue that its "on-the-fly" abstraction process transforms or compresses all data rather than selectively retaining a "sub-set" and discarding the rest, as the patent specification suggests.
  • Technical Questions: Does the complaint provide sufficient evidence that Avatar's abstraction method actually discards cell and interconnect data? The allegations are based on marketing claims of efficiency ("drastically reducing run time and memory") (Compl. ¶36, p. 18), which could be achieved through various means other than the specific claimed method of retaining a mere subset of the original data.

V. Key Claim Terms for Construction

For the ’640 Patent

  • The Term: "statistical maximum preserves N sigma corner delay values"
  • Context and Importance: This term defines the core technical function of the claimed SSTA method. The infringement analysis will depend on whether this is construed as a broad functional goal or a specific mathematical operation. Practitioners may focus on this term because it distinguishes the invention from prior art methods that might combine statistical variables without guaranteeing accuracy at a specific statistical corner.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent states a goal is to "guarantee pessimism at nominal and targeted N-sigma corner" (’640 Patent, col. 2:23-24), suggesting that any method achieving this functional outcome could fall within the claim's scope.
    • Evidence for a Narrower Interpretation: The specification provides a precise mathematical formula for the "statistical max opera-tions" (see, e.g., Equation 10) (’640 Patent, col. 7:48-56). A defendant may argue the claim is limited to this specific implementation or its direct mathematical equivalent.

For the ’863 Patent

  • The Term: "retaining only a sub-set of"
  • Context and Importance: This phrase is critical to defining the reductive nature of the claimed "abstraction." The dispute will likely involve whether Avatar's method truly filters and discards data as required, or simply transforms it.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The stated goal of the abstraction is to "reduce the amount of memory required to represent a block" and "reduce the amount of execution time" (’863 Patent, col. 4:9-14). This could support a reading where any form of effective data reduction constitutes retaining "only a sub-set."
    • Evidence for a Narrower Interpretation: The specification gives concrete examples of what is discarded, such as "cells that are completely register bounded within the block" (’863 Patent, col. 7:50-52). This suggests "retaining only a sub-set" requires a specific filtering process where some categories of data are wholly discarded, not merely compressed or transformed.

VI. Other Allegations

  • Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, stating that Avatar intentionally encourages infringement by promoting, advertising, and providing instructions and user manuals for the accused products (e.g., Compl. ¶27, ¶37). It also alleges contributory infringement, claiming the accused software is a material component of the patented methods, is not a staple article of commerce, and was especially made or adapted for an infringing use (e.g., Compl. ¶28, ¶38).
  • Willful Infringement: The complaint alleges willful infringement for all six patents, based on alleged actual knowledge from pre-suit notice letters sent by Synopsys's counsel in May and June of 2020 (e.g., Compl. ¶30, ¶40). Notably, the willfulness counts in the complaint repeatedly refer to "Real Intent" rather than the defendant, "Avatar," suggesting a possible drafting error (Compl. ¶30, ¶40, ¶50, ¶60, ¶70, ¶80).

VII. Analyst’s Conclusion: Key Questions for the Case

  • Evidentiary Sufficiency: A primary issue will be whether the plaintiff can successfully connect the defendant's high-level product descriptions and marketing claims to the specific technical steps recited in the patent claims. The infringement allegations rely heavily on public-facing documents and inferences about the accused software's functionality; the case may depend on whether discovery reveals source code and internal design documents that map directly onto the patented methods.
  • Claim Scope and Functionality: The outcome will likely turn on claim construction. For the ’640 patent, a key question is one of functional equivalence: does Aprisa's method for combining statistical delays perform the specific mathematical function required to "preserve N sigma corner delay values," or does it use a different algorithm to achieve a similar commercial goal of correlation? For the ’863 patent, the core issue is one of definitional scope: can the phrase "retaining only a sub-set" be construed to cover a process that provides "on-the-fly" data, or is it limited to a method that explicitly filters and discards specific categories of data from a static model?