Altair Logix LLC v. DFI America LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: DFI America, LLC (California)
  • Plaintiff’s Counsel: Insight, PLC
• Case Identification: 3:20-cv-06757, N.D. Cal., 09/29/2020
• Venue Allegations: Venue is alleged to be proper based on Defendant maintaining a place of business within the Northern District of California.
• Core Dispute: Plaintiff alleges that Defendant’s industrial tablet PCs, which incorporate NXP i.MX 6 series application processors, infringe a patent related to dynamically reconfigurable multi-processor architectures for media processing.
• Technical Context: The technology concerns system-on-a-chip (SoC) designs that seek to combine the high performance of fixed-function hardware with the flexibility of software-based systems for demanding multimedia applications.
• Key Procedural History: The complaint alleges that the asserted patent’s independent claim issued without amendment and that there was no rejection during prosecution contending the claim was anticipated by any prior art.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"

• Patent Identification: U.S. Patent No. 6,289,434, "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates," issued September 11, 2001.

The Invention Explained

• Problem Addressed: The patent addresses the trade-offs between different methods of implementing complex digital processing functions on silicon (Compl. ¶¶ 13-17). Traditional hard-wired, fixed-function circuits offer high performance but are inflexible and costly to design, while alternatives like microprocessors, Digital Signal Processors (DSPs), and Field-Programmable Gate Arrays (FPGAs) suffer from performance or cost limitations, particularly for tasks requiring parallel processing (’434 Patent, col. 1:42-2:33). The patent identifies "temporal redundancy"—committing silicon resources to handle all possible data processing scenarios, even those not used in a final application—as a key source of inefficiency in fixed-function systems (’434 Patent, col. 2:50-60).
• The Patented Solution: The invention proposes an apparatus with a plurality of "media processing units" (MPUs) that can be dynamically reconfigured at run-time to adapt to varying data and processing requirements (’434 Patent, col. 3:6-11). By re-using computational and storage elements in different configurations, this architecture aims to remove redundancy, thereby achieving the performance of fixed-function systems at a lower cost (Compl. ¶ 20; ’434 Patent, col. 3:1-11). The overall architecture, depicted in Figure 3 of the patent, shows multiple MPUs interconnected through a memory-mapped protocol (Compl. ¶ 23; ’434 Patent, Fig. 3).
• Technical Importance: The invention describes an architecture intended to provide a more cost-effective and flexible platform for high-performance, real-time multimedia processing on a single chip (Compl. ¶¶ 12, 20).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶ 26).
• The essential elements of Claim 1 include:
  • An apparatus with addressable memory and a plurality of media processing units (MPUs).
  • Each MPU is coupled to the memory and comprises a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit (BMU).
  • The ALU must be capable of operating concurrently with the multiplier and arithmetic unit.
  • The BMU must be capable of operating concurrently with the ALU and at least one of the multiplier or arithmetic unit.
  • The plurality of MPUs must be capable of performing operations simultaneously with each other.
  • Each operation involves receiving an instruction and data from memory, processing the data, and providing a result to the MPU input/output.

III. The Accused Instrumentality

Product Identification

• The "Freescale i.MX6 Series 10.1" Industrial Tablet PC," identified as the DFI ART101-i6 model, which incorporates the NXP i.MX 6DualLite applications processor (Compl. ¶¶ 26, 27).

Functionality and Market Context

• The complaint alleges that the NXP i.MX 6DualLite processor embodies the patented technology (Compl. ¶¶ 28-35). The processor is described as containing a "Dual ARM cortex A9 Core" and is marketed as being "particularly suited to multimedia applications" (Compl. ¶ 28; Compl. p. 11). The infringement theory centers on the processor's dual-core architecture and its integrated NEON media coprocessor, which is an advanced SIMD (Single Instruction, Multiple Data) processing unit (Compl. ¶¶ 17-18, 28). The complaint alleges the dual ARM cores constitute the "plurality of media processing units," and that the NEON coprocessor within each core contains the claimed multiplier, arithmetic unit, ALU, and bit manipulation unit (Compl. ¶¶ 29-32).

IV. Analysis of Infringement Allegations

'434 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central dispute may arise over the definition of "media processing unit." The patent describes this unit as an "aggregate of the dynamically reconfigurable computational and storage elements" (’434 Patent, col. 3:14-18) and provides a specific architecture in its figures (e.g., Fig. 3). The complaint equates this term with a general-purpose, off-the-shelf ARM Cortex-A9 processor core. The case may turn on whether the patent’s specific, seemingly custom architecture can be read to cover a standard CPU core with a SIMD coprocessor.
  • Technical Questions: The complaint asserts that the various sub-units (multiplier, ALU, etc.) within the NEON coprocessor operate "concurrently" as required by the claim (Compl. ¶¶ 31-32). A key technical question for the court will be what level of proof is required to show this specific concurrency. The infringement analysis may depend on whether the pipelined, superscalar nature of the ARM architecture inherently satisfies the claim’s concurrency limitations, or if a more specific, simultaneous mode of operation is required that the accused product does not perform.

V. Key Claim Terms for Construction

• The Term: "media processing unit"

• Context and Importance: This term is the core building block of the claimed invention. Its construction will be critical to determining if the accused ARM Cortex-A9 processor falls within the scope of the patent. Practitioners may focus on this term because the patent appears to describe a bespoke, reconfigurable architecture, while the accused product uses a widely licensed, general-purpose CPU core.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent's abstract describes processors that "perform arithmetic-type functions, logic functions and bit manipulation functions" operating under a stored program, language which could plausibly describe a general-purpose CPU (’434 Patent, Abstract).
  • Evidence for a Narrower Interpretation: The specification defines the term as the "aggregate of the dynamically reconfigurable computational and storage elements" (’434 Patent, col. 3:14-16) and repeatedly emphasizes its "RISC-like nature" and ability to be reconfigured "on the fly" to "emulate fixed-function (hard-wired) designs" (’434 Patent, col. 4:5-7, col. 3:9-10). The embodiment in Figure 3 shows a specific "MEDIA PROCESSOR" block with dedicated instruction cache and data RAM, which may support a narrower construction limited to architectures that mirror this specific structure.

• The Term: "concurrently"

• Context and Importance: Claim 1 requires two separate instances of concurrent operation among the sub-units of the MPU. The infringement analysis will depend heavily on whether the normal, pipelined operation of the accused NEON unit meets this limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent does not explicitly define "concurrently" in a way that would exclude modern, superscalar processor operations where multiple instructions are in different stages of execution at the same time. Plaintiff may argue that any parallel execution within the processor pipeline satisfies this term.
  • Evidence for a Narrower Interpretation: A defendant could argue that the claim language requires the specified units (e.g., the ALU and the multiplier) to be capable of executing independent instructions simultaneously in the same clock cycle, not just in an overlapping, pipelined fashion. The patent states that a complex instruction may configure the MPU "to execute three concurrent 32 bit arithmetic or logical operations in parallel...all this in a single clock cycle," which could support a requirement for true single-cycle parallelism (’434 Patent, col. 4:39-44).

VI. Other Allegations

The complaint contains a single count for "Patent Infringement" focused on direct infringement. It does not plead sufficient facts to support separate allegations of indirect or willful infringement. Paragraph 37 alleges constructive notice of the patent via operation of law, which is a prerequisite for damages but does not, on its own, establish the knowledge required for willfulness.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "media processing unit", which the patent describes as a "dynamically reconfigurable" architecture, be construed to cover a standard, general-purpose ARM Cortex-A9 CPU core and its associated NEON SIMD coprocessor?
• A key evidentiary question will be one of functional operation: does the accused processor’s architecture meet the specific "concurrently" operating limitations of Claim 1? The resolution will likely depend on whether the claim requires true single-cycle parallelism between distinct functional units or if the inherent pipelining of a modern processor is sufficient to infringe.