DCT

3:23-cv-01001

Semiconductor Design Tech LLC v. Cadence Design Systems Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:23-cv-01001, N.D. Cal., 06/29/2023
  • Venue Allegations: Plaintiff alleges venue is proper in the Northern District of California because Defendant maintains a regular and established place of business, including its principal executive offices, within the district and has committed alleged acts of infringement there, such as testing and customer support for the accused software.
  • Core Dispute: Plaintiff alleges that Defendant’s Electronic Design Automation (EDA) software for high-level synthesis infringes patents related to automatically generating circuit design assertions and analyzing design latency.
  • Technical Context: The technology involves EDA tools, which are fundamental software platforms used in the multi-billion dollar semiconductor industry to design and verify complex integrated circuits before costly manufacturing.
  • Key Procedural History: The complaint alleges that the patents' former owner, Ricoh Company, Ltd., sent letters to Defendant in November and December 2020, providing pre-suit notice of the patents-in-suit. The complaint also asserts that Defendant had knowledge of the '636 patent because it was cited as prior art during the prosecution of several of Defendant's own patents.

Case Timeline

Date Event
2004-09-30 U.S. Patent No. 7,603,636 Priority Date
2007-02-19 U.S. Patent No. 7,971,167 Priority Date
2009-10-13 U.S. Patent No. 7603636 Issues
2011-06-28 U.S. Patent No. 7971167 Issues
2020-11-02 Ricoh letter to Cadence regarding patents-in-suit alleged
2020-12-11 Ricoh letter to Cadence regarding patents-in-suit alleged
2023-06-29 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,603,636 - "Assertion Generating System, Program Thereof, Circuit Verifying System, and Assertion Generating Method," Issued October 13, 2009

The Invention Explained

  • Problem Addressed: The patent addresses inefficiencies and errors in verifying semiconductor circuit designs. Manually writing "assertions"—code snippets that check if a design behaves as intended—is prone to human error. Existing automated methods that derive assertions from a Register-Transfer Level (RTL) description are also problematic because the RTL itself is the object being verified and may not accurately reflect the original design intent. ('636 Patent, col. 3:43-53, col. 4:4-19).
  • The Patented Solution: The invention proposes a system to automatically generate verification assertions directly from the high-level circuit specification. A user employs a graphical editor to define the specification (e.g., as a state transition figure), which the system then uses to automatically extract "properties" and convert them into an assertion description language for use in a simulator. ('636 Patent, Abstract; Fig. 2). This method aims to ensure that the verification logic is faithful to the original design specification, rather than a potentially flawed intermediate design stage. ('636 Patent, col. 6:49-59).
  • Technical Importance: By automating the creation of assertions from the primary specification, this approach was intended to improve verification accuracy and reduce the time spent debugging both the circuit design and the verification code itself. (Compl. ¶27).

Key Claims at a Glance

  • The complaint asserts independent claim 8. (Compl. ¶45).
  • Essential elements of claim 8, which covers a computer-readable medium, include programming a computer to perform steps of:
    • A specification inputting step that generates design data by graphically editing a specification of the semiconductor integrated circuit.
    • A property generating step that reads the generated design data from storage and generates a property verifying the specification.
    • An assertion generating step that reads the property from storage and converts it into an assertion description for verification.
    • The generated property being a selection condition related to a state transition, a logic value of signals, or signals in the design data.

U.S. Patent No. 7,971,167 - "Semiconductor Design Support Device, Semiconductor Design Support Method, and Manufacturing Method for Semiconductor Integrated Circuit," Issued June 28, 2011

The Invention Explained

  • Problem Addressed: In the high-level synthesis workflow, a high-level "behavioral description" of a circuit is converted into a more detailed "RTL description." If a simulation of the RTL reveals high latency (i.e., processing delay), it is difficult for designers to trace that latency back to the specific part of the original, more abstract behavioral code that caused it. ('167 Patent, col. 1:48-55; Compl. p.10 ¶¶1-2).
  • The Patented Solution: The invention describes a design support device featuring a "latency analyzer" and a "correspondence table generator." The generator creates a table that explicitly maps blocks of code in the high-level behavioral description to corresponding states in the low-level RTL description. After running an RTL simulation, the latency analyzer uses this table to pinpoint which high-level behavioral blocks are responsible for the measured latency, allowing designers to efficiently target their optimization efforts. (’167 Patent, Abstract; Fig. 1).
  • Technical Importance: This system provides designers with granular, block-by-block insight into the performance implications of their high-level design choices, a functionality the complaint alleges was previously unavailable. (Compl. ¶37).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶76).
  • Essential elements of claim 1, which covers a design support device, include:
    • A behavioral description of a processing algorithm.
    • An RTL description generated from the behavioral description.
    • A latency analyzer to calculate latency in each behavioral block by analyzing a simulation of the RTL description.
    • A correspondence table mapping each behavioral block to a state in the RTL description.
    • A correspondence table generator to create the correspondence table.

III. The Accused Instrumentality

Product Identification

  • Cadence Stratus HLS (High-Level Synthesis) software. (Compl. ¶44, ¶75).

Functionality and Market Context

  • The complaint describes Stratus HLS as an EDA software tool that automates the creation of RTL design implementations from high-level descriptions written in languages like SystemC and C++. (Compl. ¶80). Its alleged functionality includes a graphical user interface (GUI) for design and analysis, synthesis of high-level assertions into standard verification languages (SystemVerilog Assertions), and analysis of design performance metrics like latency. (Compl. ¶62, ¶68, ¶87). The complaint positions the accused product within the approximately $4 billion U.S. EDA software market and identifies Cadence as a global supplier. (Compl. ¶5, ¶13).

IV. Analysis of Infringement Allegations

’636 Patent Infringement Allegations

Claim Element (from Independent Claim 8) Alleged Infringing Functionality Complaint Citation Patent Citation
a specification inputting step that generates design data of the semiconductor integrated circuit by graphically editing a specification of the semiconductor integrated circuit based on user operations The Stratus HLS software provides a GUI with an IDE where users create and edit design models (e.g., in SystemC), which the complaint characterizes as graphically editing a specification. A provided screenshot shows the Stratus IDE with source code and graphical analysis panes. (Compl. p.18, Fig. 2). ¶62 col. 6:49-59
a property generating step that reads the design data generated at the specification inputting step from the storage and generates a property which verifies the specification of the semiconductor integrated circuit The Stratus HLS software is alleged to read the user-created design data and generate verification properties by, for example, synthesizing SystemC assertions into the generated RTL. A provided diagram shows a flow from a behavioral assertion to a synthesized RTL assertion. (Compl. p.21, Fig. 5). ¶64, ¶65 col. 7:10-21
an assertion generating step that reads the property generated at the property generating step from the storage and converts the property into an assertion description if the property is to be verified during assertion verification Stratus HLS allegedly converts the generated property (e.g., the SystemC assertion) into a standard assertion description (a SystemVerilog assertion, or SVA) that can be used by verification tools. ¶68 col. 7:22-30
the property generated...is a selection condition with respect to a state transition, a logic value of at least one or more signals, or at least one or more signals in the design data The complaint alleges that the properties and assertions generated by Stratus HLS describe design conditions related to state transitions, logic values, and signals. ¶69 col. 7:52-59
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether entering text-based SystemC code into an IDE, as shown in the complaint's evidence (Compl. p.19), constitutes "graphically editing a specification." The defense may argue this term, in the context of the ’636 patent’s disclosure of state transition figures, requires manipulation of visual diagrams, not just text entry within a GUI.
    • Technical Questions: The analysis may focus on whether the accused "synthesis of SystemC assertions" is technically equivalent to the claimed "property generating step." The inquiry will likely examine if the accused feature reads design data from the graphically edited specification to generate verification logic, as the claim requires, or if it operates on a different data source.

’167 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a behavioral description configured to describe an algorithm of processing performed by hardware in a motion level Stratus HLS is alleged to receive, store, and process behavioral descriptions in the form of SystemC and C++ models. ¶81 col. 5:4-6
an RTL description generated by reading the behavioral description... The core function of the Stratus HLS tool is alleged to be generating an RTL description from a high-level behavioral description. A provided diagram illustrates this synthesis flow. (Compl. p.32, Fig. 1). ¶82 col. 5:7-11
a latency analyzer configured to analyze a result of a logic simulation performed on the RTL description to calculate a latency in each block... Stratus HLS is alleged to include a latency analyzer that uses its "Genus Synthesis Solution engine" to perform timing-aware synthesis and calculate latency for different blocks of the design. The software GUI allegedly displays this latency information. ¶84, ¶87 col. 5:12-17
a correspondence table in which each block in the behavioral description corresponds to a state in the RTL description The complaint alleges Stratus HLS includes this functionality via its "rtl_annotation" feature, which enables tracing of RTL code lines back to the originating behavioral SystemC source code. A diagram shows this traceability. (Compl. p.40, Fig. 9). ¶88, ¶90 col. 5:18-21
a correspondence table generator configured to generate the correspondence table The complaint alleges Stratus HLS generates this correspondence by supporting graphical analysis of RTL with links back to the source code, thereby generating the claimed table. ¶91 col. 5:22-24
  • Identified Points of Contention:
    • Scope Questions: The infringement analysis will likely turn on whether the accused product's "traceability" and "RTL annotation" features (Compl. ¶90) meet the definition of a "correspondence table." The defense may argue the patent requires an explicit data structure mapping behavioral blocks to RTL states, as depicted in its Figure 3, whereas the complaint's evidence may show a more general-purpose line-level debugging link.
    • Technical Questions: A key question is whether Stratus HLS generates a discrete "correspondence table" as a data structure or whether the mapping is an implicit, transient function of its debug and analysis tools. The evidence required to prove the existence and generation of the claimed "table" will be a focal point.

V. Key Claim Terms for Construction

  • For the ’636 Patent:
    • The Term: "graphically editing a specification"
    • Context and Importance: This term defines the initial step of the claimed process and is a potential point of non-infringement. The dispute will likely focus on whether editing text-based source code within a GUI falls within the scope of this term.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claims do not explicitly restrict the term to visual diagrams. Plaintiff may argue that any user interaction to create or modify a specification within a graphical user interface, even via a text editor pane, constitutes "graphical editing."
      • Evidence for a Narrower Interpretation: The patent’s abstract and detailed description repeatedly reference editing specifications using a "state transition table and a state transition figure" or a "timing chart." ('636 Patent, Abstract; col. 8:14-19). This may support an argument that the term is limited to the manipulation of visual, non-textual design elements.
  • For the ’167 Patent:
    • The Term: "correspondence table"
    • Context and Importance: This term is the central element linking the behavioral and RTL domains. The viability of the infringement claim depends on whether the accused product's traceability feature functions as this "table."
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim language defines the table by its function: one "in which each block in the behavioral description corresponds to a state in the RTL description." (’167 Patent, cl. 1). Plaintiff may argue that any data, structure, or mechanism that achieves this mapping, regardless of its format, is a "correspondence table."
      • Evidence for a Narrower Interpretation: The patent provides a specific embodiment of the table in Figure 3, which has distinct columns for "BLOCK NAME," "START STATE," and "FINISH STATE." (’167 Patent, Fig. 3). The defense could argue that the term should be construed to require this explicit, tabular structure, which may differ from the code annotation feature shown in the complaint's evidence. (Compl. p.40, Fig. 9).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement. It alleges inducement is based on Defendant advertising the Accused Products and providing instruction manuals, training, and support to customers, knowing this would cause infringement. (Compl. ¶70, ¶93). It alleges contributory infringement on the basis that the Accused Products are especially designed to infringe and are not a staple of commerce suitable for substantial non-infringing use. (Compl. ¶71, ¶94).
  • Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. Pre-suit knowledge is alleged based on notice letters sent by the patents' former owner to Defendant in 2020 and, for the ’636 patent, its citation in Defendant's own patent prosecution files. (Compl. ¶47, ¶48, ¶78). Post-suit knowledge is based on the filing of the lawsuit. (Compl. ¶46).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "graphically editing a specification" from the ’636 patent, which is described in the context of visual state-transition figures, be construed to cover the act of writing source code in a text editor within the accused product’s graphical IDE?
  • A key evidentiary question will be one of structural equivalence: do the accused product's code annotation and traceability features constitute the "correspondence table" required by the ’167 patent, or does the claim require a more formally structured, table-like data mapping behavioral blocks to specific RTL states?
  • The allegations of pre-suit notice through letters and patent citations raise a significant question of knowledge and intent, making the factual record surrounding Defendant's awareness of the patents central to the claims for willful and indirect infringement.