DCT

3:23-cv-05792

Yangtze Memory Tech Co Ltd v. Micron Technology Inc

Log In
Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:23-cv-05792, U.S. District Court for the Northern District of California (N.D. Cal.), 10/09/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant Micron maintains a regular and established place of business in the district, specifically in San Jose, California, and has committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s 3D NAND and DRAM memory products infringe a broad portfolio of nineteen U.S. patents related to semiconductor memory device architecture, fabrication methods, and operation.
  • Technical Context: 3D NAND flash memory is a critical technology for increasing data storage density and reducing cost-per-bit in a wide range of products, from consumer electronics to enterprise data centers.
  • Key Procedural History: This action is a consolidation of two separate lawsuits filed by YMTC against Micron. The first, "YMTC I," was filed on November 9, 2023. The second, "YMTC II," asserting a different set of patents, was filed on July 12, 2024. The Court granted a motion to consolidate the cases on August 21, 2024, leading to this First Amended Consolidated Complaint. The complaint also notes that Micron has previously cited certain YMTC patents as relevant prior art during the prosecution of its own patent applications, a fact that may be relevant to allegations of pre-suit knowledge.

Case Timeline

Date Event
2018-05-03 Priority Date for U.S. Patent No. 10,658,378
2018-05-11 Priority Date for U.S. Patent No. 10,950,623
2019-05-28 Priority Date for U.S. Patent No. 10,879,254
2019-05-31 Priority Date for U.S. Patent No. 10,861,872
2019-06-28 Priority Date for U.S. Patent No. 10,886,291
2019-07-02 Priority Date for U.S. Patent No. 10,868,031
2020-05-19 U.S. Patent No. 10,658,378 Issued
2020-06-02 U.S. Patent No. 10,672,711 Issued
2020-07-27 Priority Date for U.S. Patent No. 11,501,822
2020-12-08 U.S. Patent No. 10,861,872 Issued
2020-12-15 U.S. Patent No. 10,868,031 Issued
2020-12-29 U.S. Patent Nos. 10,879,254 and 10,879,164 Issued
2021-01-05 U.S. Patent No. 10,886,291 Issued
2021-03-02 U.S. Patent No. 10,937,806 Issued
2021-03-16 U.S. Patent No. 10,950,623 Issued
2021-05-06 Micron cites YMTC's '031 Patent as prior art in a U.S. Patent Application prosecution
2021-08-24 U.S. Patent No. 11,101,276 Issued
2021-10-12 U.S. Patent No. 11,145,666 Issued
2022-09-20 U.S. Patent No. 11,450,604 Issued
2022-10-11 U.S. Patent No. 11,468,957 Issued
2022-10-25 U.S. Patent No. 11,482,532 Issued
2022-11-15 U.S. Patent No. 11,501,822 Issued
2023-01-31 U.S. Patent No. 11,568,941 Issued
2023-02-14 U.S. Patent No. 11,581,322 Issued
2023-03-07 U.S. Patent No. 11,600,342 Issued
2023-11-09 Original "YMTC I" Complaint Filed
2024-06-11 U.S. Patent No. 12,010,838 Issued
2024-07-12 "YMTC II" Complaint Filed
2024-08-21 Court Consolidates YMTC I and YMTC II Cases
2024-10-09 First Amended Consolidated Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,950,623 - “3D NAND Memory Device and Method of Forming the Same”

Issued March 16, 2021

The Invention Explained

  • Problem Addressed: The patent addresses challenges in manufacturing 3D NAND memory, specifically related to forming common source regions and mitigating parasitic capacitance that can degrade device performance. As memory stacks become taller and denser, controlling the electrical characteristics of components like the bottom select gate (BSG) becomes more difficult ('623 Patent, col. 1:12-40).
  • The Patented Solution: The invention describes a 3D NAND device structure that includes "first dielectric trenches" formed in the bottom select gate layer. These trenches, filled with a dielectric material, physically separate the BSG into a plurality of "sub-BSGs" ('623 Patent, col. 2:1-8). This segmentation is designed to reduce parasitic capacitance and coupling effects, thereby improving the performance of the memory device ('623 Patent, col. 2:1-8). The patent's Figure 1A illustrates this structure, showing separate sub-BSG regions (62p-1, 62p-2, 62p-3) divided by first dielectric trenches (26, 28).
  • Technical Importance: This approach of segmenting gate layers using dielectric trenches allows for more precise electrical control over different sections of the memory array, which can improve data transfer speeds and reduce errors in high-density memory chips ('623 Patent, col. 2:1-8).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶43).
  • The essential elements of Claim 1 include:
    • A substrate.
    • A bottom select gate (BSG) disposed over the substrate.
    • A plurality of word lines positioned over the BSG with a staircase configuration.
    • A plurality of insulating layers disposed between the substrate, the BSG, and the word lines.
    • One or more first dielectric trenches formed in the BSG, extending in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs.
    • One or more common source regions formed over the substrate and extending in the length direction, where these regions extend through the BSG, word lines, and insulating layers.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 11,501,822 - “Non-Volatile Memory Device and Control Method”

Issued November 15, 2022

The Invention Explained

  • Problem Addressed: As the number of layers in 3D NAND devices increases, "program disturb" becomes a more significant problem. This occurs when the process of programming one memory cell unintentionally affects the stored charge in neighboring cells, leading to data errors. A "pre-pulse signal" applied to an unselected bit line can help mitigate this, but its effectiveness diminishes with increased channel length in taller memory stacks ('822 Patent, col. 1:26-44).
  • The Patented Solution: The patent discloses a control method that uses a series of "word line pre-pulse signals" with incrementally increasing voltage levels. These pulses are applied to word lines between the selected word line and the select gate during a pre-charge period (’822 Patent, col. 2:1-12). This graduated voltage scheme is designed to more effectively counteract program disturb without requiring an excessively long pre-charge time or risking damage from a single high-voltage pulse (’822 Patent, Abstract; Fig. 5).
  • Technical Importance: This method offers a more nuanced way to manage electrical conditions within a memory string during programming, potentially improving reliability and programming speed for high-density, multi-layered 3D NAND devices (’822 Patent, col. 2:1-12).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶54).
  • The essential elements of Claim 1 include:
    • A memory device with a memory array, a bit line, a select gate line, and a plurality of word lines.
    • A control circuit configured to apply a bit line pre-pulse signal during a pre-charge period.
    • The control circuit is also configured to apply a word line signal to a selected word line and a plurality of word line pre-pulse signals to word lines between the select gate line and the selected word line.
    • A key limitation is that the "voltage levels of the plurality of word line pre-pulse signals are incremental."
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 10,658,378 - “Through Array Contact (TAC) for Three-Dimensional Memory Devices”

Issued May 19, 2020

  • Technology Synopsis: This patent addresses the challenge of creating reliable vertical interconnects, known as Through Array Contacts (TACs), in 3D memory devices. The invention describes a 3D memory device with a TAC that extends vertically through a "single-material" dielectric structure, which simplifies fabrication compared to etching through alternating layers of different materials ('378 Patent, Abstract; col. 2:51-57).
  • Asserted Claims: Claim 15 is asserted (Compl. ¶65).
  • Accused Features: The complaint alleges that Micron's 128L, 176L, and 232L Accused Products contain TAC structures that infringe the ’378 Patent (Compl. ¶65).

U.S. Patent No. 10,861,872 - “Three Dimensional Memory Device and Methods for Forming the Same”

Issued December 8, 2020

  • Technology Synopsis: This patent relates to the structural layout of 3D memory devices, focusing on the placement of "dummy source structures" that surround a staircase contact. These dummy structures are intended to improve the uniformity of the fabrication process, particularly etching, which can enhance device performance and yield ('872 Patent, col. 10:4-15; Abstract).
  • Asserted Claims: Claim 1 is asserted (Compl. ¶89).
  • Accused Features: Micron's 128L, 176L, and 232L Accused Products are alleged to incorporate infringing dummy structures as claimed (Compl. ¶89).

III. The Accused Instrumentality

Product Identification

The accused products are Micron's 96-Layer ("96L"), 128-Layer ("128L"), 176-Layer ("176L"), and 232-Layer ("232L") 3D NAND flash memory chips, as well as its DDR5 DRAM memory chips (Compl. ¶¶24-28). The complaint collectively refers to these as the "Accused Memory Products" (Compl. ¶29).

Functionality and Market Context

The Accused Memory Products are semiconductor components that provide high-density, non-volatile data storage. They are integrated into a wide array of electronic devices, including smartphones, laptops, data centers, and enterprise storage solutions (Compl. ¶4). The complaint alleges that these products are essential components for modern digital devices and that Micron is a major global manufacturer and supplier (Compl. ¶¶4, 23). The complaint further alleges that YMTC is a "key player in the global 3D NAND market" and that Micron is "threatened by YMTC's ascension" (Compl. ¶3).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

The complaint incorporates by reference exemplary claim charts as exhibits (e.g., Exs. 46-62), but these exhibits were not filed with the complaint document. Accordingly, the infringement theories are summarized below in prose based on the narrative allegations.

’623 Patent Infringement Allegations

  • Infringement Theory: The complaint alleges that Micron's 96L Accused Products, such as the Micron SSD models 1300 SATA and c200, directly and indirectly infringe at least claim 1 of the ’623 Patent (Compl. ¶¶43, 46). The infringement theory appears to center on the physical structure of the accused memory chips. The complaint specifically notes that its claim chart exhibit (Exhibit 46) "shows precisely where the claimed dielectric trenches can be found, and their orientation," suggesting the infringement allegation is based on the presence and specific arrangement of dielectric trenches used to segment the bottom select gate in the accused products (Compl. ¶45).
  • Identified Points of Contention: The core dispute may center on claim construction and structural analysis. A key question will be whether the structures identified by YMTC in Micron's products constitute "first dielectric trenches" that "separate the BSG into a plurality of sub-BSGs" as required by claim 1. Micron's response to an earlier version of the complaint, as characterized by YMTC, disputed the identification of these claimed trenches, suggesting that the existence, orientation, and function of these structures in the accused products will be a central point of contention (Compl. ¶45).

’822 Patent Infringement Allegations

  • Infringement Theory: The complaint alleges that Micron's 176L and 232L Accused Products, such as the Micron SSD models 3400 NVMe and 2550, directly and indirectly infringe at least claim 1 of the ’822 Patent (Compl. ¶¶54, 57). The infringement theory focuses on the operational method of the accused devices, specifically the voltage signals applied during programming. The complaint alleges that the accused products use a control method that applies "word line pre-pulse signals" with "incremental" voltage levels, as required by the patent (Compl. ¶55; ’822 Patent, cl. 1). YMTC states its claim chart exhibits (Exhibits 47-48) counter Micron's earlier assertion that the complaint failed to plead sufficient factual detail regarding these voltage levels (Compl. ¶56).
  • Identified Points of Contention: The dispute will likely involve detailed technical analysis of the voltage waveforms used in the accused products. A central question will be whether the pre-pulse signals used by Micron's devices meet the "incremental" voltage level limitation of claim 1. This could turn on both the definition of "incremental" and the evidentiary proof of the precise voltage application schemes employed by the accused chips.

V. Key Claim Terms for Construction

For the ’623 Patent

  • The Term: "first dielectric trenches... separat[ing] the BSG into a plurality of sub-BSGs"
  • Context and Importance: The definition of this structural arrangement is central to the infringement analysis. The complaint suggests this was a point of dispute in earlier pleadings (Compl. ¶45). Practitioners may focus on this term because the dispute will likely involve whether the structures in Micron's chips perform the same function (separation of the BSG) in the same way as described in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the benefit as reducing process complexity and manufacturing cost, which could support an argument that any structure achieving this benefit falls within the claim scope ('623 Patent, col. 5:41-45).
    • Evidence for a Narrower Interpretation: Figure 1A of the patent shows distinct, fully separated sub-BSG regions (62p-1, 62p-2, 62p-3) divided by the trenches (26, 28). This specific embodiment could be used to argue for a narrower construction requiring complete physical and electrical separation into discrete sub-gates.

For the ’822 Patent

  • The Term: "voltage levels of the plurality of word line pre-pulse signals are incremental"
  • Context and Importance: This term defines the core technical innovation of the claimed method. The dispute will turn on whether the accused devices' voltage schemes meet this "incremental" requirement. The complaint highlights this as a feature detailed in its claim chart exhibits, suggesting it is a known point of contention (Compl. ¶56).
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent abstract states the voltage levels are "incremental," and the detailed description refers to a "first word line pre-pulse signal" and a "second word line pre-pulse signal" where the second has a voltage level "greater than" the first (’822 Patent, Abstract; col. 3:15-22). This could support a reading that requires only a general, stepwise increase in voltage.
    • Evidence for a Narrower Interpretation: Figure 5 of the patent provides a specific, detailed waveform diagram showing three distinct, sequentially rising voltage levels (VP_BOTTOMWL, VP_MIDDLEWL, VP_TOPWL). This could support an argument that "incremental" requires a specific, multi-step, monotonically increasing voltage sequence as depicted, rather than any general increase.

VI. Other Allegations

Indirect Infringement

The complaint alleges that Micron induces infringement by "actively encouraging others to infringe" (Compl. ¶46, ¶57). This is allegedly done through the publication and provision of technical materials, product specifications, and promotional literature that instruct customers and third parties on how to integrate and use the Accused Memory Products in an infringing manner (Compl. ¶47, ¶58).

Willful Infringement

Willfulness is alleged based on Micron's continued infringement since at least the filing of the original complaint on November 9, 2023, which allegedly put Micron on notice (Compl. ¶48, ¶59). The complaint also alleges potential pre-suit knowledge, pointing to instances where Micron cited YMTC's asserted patents as relevant prior art during the prosecution of its own patent applications, suggesting awareness of YMTC's technology (Compl. ¶37).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of structural correspondence: Do the physical structures within Micron's 3D NAND devices, particularly trenches and contacts, meet the specific architectural limitations of patents like the '623 and '378 patents, or do they represent a distinct, non-infringing design?
  • A key evidentiary question will be one of operational equivalence: Does the precise sequence and voltage levels of electrical pulses used to program Micron's memory chips, as targeted by patents like the '822 patent, perform the same function in substantially the same way as claimed, or is there a fundamental mismatch in the control methodology?
  • A significant legal and factual question will concern knowledge and intent: What evidence, such as Micron's citation of YMTC patents as prior art, demonstrates pre-suit knowledge of the asserted patents, and how will this impact the claims for willful infringement?