DCT

3:23-cv-05792

Yangtze Memory Tech Co Ltd v. Micron Technology Inc

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:23-cv-05792, N.D. Cal., 02/02/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Northern District of California because Defendants maintain a regular and established place of business in San Jose, California, and because 3D NAND-related design and product engineering for the accused products occurs at Defendants' facilities within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s 3D NAND flash memory products infringe eight U.S. patents related to semiconductor device architecture, fabrication methods, and operation.
  • Technical Context: 3D NAND is a type of flash memory that stacks memory cells vertically to achieve higher storage densities than traditional planar NAND, and it is a foundational technology for modern data storage in consumer electronics and enterprise systems.
  • Key Procedural History: The action was initiated on November 9, 2023. After Defendants moved to dismiss the original complaint on procedural grounds, Plaintiff filed this First Amended Complaint on February 2, 2024, to provide more detailed, claim-chart-based infringement allegations. The complaint alleges pre-suit knowledge of certain patents-in-suit based on their citation during the prosecution of Defendants' own patent applications.

Case Timeline

Date Event
2018-05-03 Priority Date for ’378 and ’806 Patents
2018-09-10 Priority Date for ’031 Patent
2019-02-26 Priority Date for ’872 Patent
2020-05-19 ’378 Patent Issued
2020-12-08 ’872 Patent Issued
2020-12-15 ’031 Patent Issued
2021-01-13 Priority Date for ’342 Patent
2021-03-02 ’806 Patent Issued
2021-03-16 ’623 Patent Issued
2021-03-04 Priority Date for ’957 Patent
2021-05-06 Micron allegedly cites ’031 Patent during prosecution of its own patent application
2021-11-01 Priority Date for ’822 Patent
2022-10-11 ’957 Patent Issued
2022-11-15 ’822 Patent Issued
2022-12-09 USPTO examiner allegedly cites ’378 Patent against a pending Micron patent application
2023-03-07 ’342 Patent Issued
2023-11-09 Original Complaint Filed
2024-02-02 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,658,378 - Through Array Contact (TAC) for Three-Dimensional Memory Devices (Issued May 19, 2020)

The Invention Explained

  • Problem Addressed: As semiconductor memory transitions from planar to 3D architectures to increase density, creating the necessary vertical electrical connections becomes increasingly complex and costly (U.S. Patent No. 10,658,378, col. 1:21-34). Fabricating these interconnects through stacks of alternating conductive and dielectric layers presents significant manufacturing challenges (’378 Patent, col. 2:21-25).
  • The Patented Solution: The invention proposes forming vertical interconnects, called “through array contacts” or TACs, within a uniform dielectric structure rather than through the complex alternating stack of the memory array itself (’378 Patent, Abstract). By etching an opening through the alternating layers down to an underlying isolation region and filling it with a single dielectric material, the subsequent formation of the conductive TAC is simplified, as it only needs to penetrate this uniform dielectric (’378 Patent, col. 2:52-58, FIG. 7).
  • Technical Importance: This method of creating vertical interconnects aims to reduce the complexity and cost of manufacturing high-density 3D NAND memory by simplifying the etching process for critical contacts (’378 Patent, col. 5:38-41).

Key Claims at a Glance

  • The complaint asserts at least independent claim 15 (Compl. ¶66).
  • Claim 15 essential elements:
    • A three-dimensional (3D) memory device, comprising:
    • a substrate with an isolation structure;
    • an alternating conductor/dielectric layer stack disposed on the substrate;
    • a dielectric structure on the isolation structure and extending vertically through the alternating conductor/dielectric layer stack, where the stack abuts a sidewall of the dielectric structure and the dielectric structure is formed of a dielectric material;
    • channel structures and slit structures extending vertically through the alternating conductor/dielectric layer stack;
    • a staircase structure disposed in the alternating conductor/dielectric layer stack; and
    • through array contacts (TACs) extending vertically through the dielectric and the isolation structures.

U.S. Patent No. 10,861,872 - Three Dimensional Memory Device and Methods for Forming the Same (Issued December 8, 2020)

The Invention Explained

  • Problem Addressed: The fabrication of 3D memory devices involves creating numerous high-aspect-ratio vertical channels and contacts. The patent notes that the etching processes used to form these structures can be non-uniform, particularly when forming features with different dimensions or in different regions of the device, which can lead to manufacturing defects (U.S. Patent No. 10,861,872, col. 1:26-38).
  • The Patented Solution: The invention describes a 3D memory device architecture that incorporates “dummy source structures” in the staircase region of the memory array (’872 Patent, Abstract). These non-functional structures are strategically placed to surround the electrically functional “staircase contact,” creating a more uniform local environment for the complex etching and deposition processes, which can improve process stability (’872 Patent, col. 2:37-46, FIG. 1A).
  • Technical Importance: The use of dummy structures is a known technique in semiconductor manufacturing to improve process uniformity and control, which is critical for achieving high yields in fabricating dense, vertically-stacked devices like 3D NAND flash memory (Compl. ¶27).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶88).
  • Claim 1 essential elements:
    • A three-dimensional (3D) memory device, comprising:
    • a substrate;
    • a memory stack including interleaved conductive layers and dielectric layers on the substrate;
    • a staircase structure on one side of the memory stack;
    • a staircase contact in the staircase structure; and
    • a plurality of dummy source structures each extending vertically through the staircase structure, wherein the plurality of dummy source structures surround the staircase contact.

Multi-Patent Capsules

  • U.S. Patent No. 10,950,623, 3D NAND Memory Device and Method of Forming the Same, Issued March 16, 2021
    • Technology Synopsis: This patent appears to address the architecture of 3D NAND memory, focusing on the configuration of dielectric trenches used to separate different sections of the memory array.
    • Asserted Claims: At least claim 1 (Compl. ¶46).
    • Accused Features: The complaint alleges that Micron's 96L Accused Products, such as the Micron SSD model 1300 SATA, incorporate the claimed dielectric trench structures and orientations (Compl. ¶46, 48).
  • U.S. Patent No. 11,501,822, Non-Volatile Memory Device and Control Method, Issued November 15, 2022
    • Technology Synopsis: This patent describes a control method for operating a non-volatile memory device, specifically relating to the voltage levels of pre-pulses applied to word lines during operation.
    • Asserted Claims: At least claim 1 (Compl. ¶56).
    • Accused Features: The complaint alleges that Micron's 176L and 232L Accused Products, such as the Micron SSD model 3400 NVMe, use a control method that satisfies the claimed voltage level limitations for word line pre-pulses (Compl. ¶56, 58).
  • U.S. Patent No. 10,937,806, Through Array Contact (TAC) for Three-Dimensional Memory Devices, Issued March 2, 2021
    • Technology Synopsis: Similar to the ’378 Patent, this patent relates to the formation and structure of through array contacts (TACs) used as vertical interconnects in 3D memory devices.
    • Asserted Claims: At least claim 8 (Compl. ¶77).
    • Accused Features: The complaint alleges that Micron's 128L, 176L, and 232L Accused Products contain the claimed TAC region (Compl. ¶77, 79).
  • U.S. Patent No. 11,468,957, Architecture and Method for NAND Memory Operation, Issued October 11, 2022
    • Technology Synopsis: This patent appears to describe a specific architecture and method for operating NAND memory, focusing on the application of particular voltages during memory operations.
    • Asserted Claims: At least claim 1 (Compl. ¶98).
    • Accused Features: The complaint alleges that Micron's 176L Accused Products are configured to apply voltages in a manner that meets the claimed voltage limitations (Compl. ¶98, 100).
  • U.S. Patent No. 11,600,342, Method for Reading Three-Dimensional Flash Memory, Issued March 7, 2023
    • Technology Synopsis: This patent describes a method for reading data from a 3D flash memory device, which involves applying varying voltages during different periods of the read operation.
    • Asserted Claims: At least claim 1 (Compl. ¶108).
    • Accused Features: The complaint alleges that Micron's 176L and 232L Accused Products utilize a read method that applies varying voltages as claimed (Compl. ¶108, 110).
  • U.S. Patent No. 10,868,031, Multiple-Stack Three-Dimensional Memory Device And Fabrication Method Thereof, Issued December 15, 2020
    • Technology Synopsis: This patent relates to the structure and fabrication of 3D memory devices built with multiple vertically stacked memory arrays, focusing on a supporting pillar structure with aligned sidewall surfaces.
    • Asserted Claims: At least claim 1 (Compl. ¶118).
    • Accused Features: The complaint alleges that Micron's 128L and 176L Accused Products contain the claimed supporting pillar structure (Compl. ¶118, 120).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Micron’s 96-Layer, 128-Layer, 176-Layer, and 232-Layer 3D NAND memory chips, and products that incorporate these chips, such as solid-state drives (SSDs) sold under the Micron and Crucial brand names (collectively, the “Accused Memory Products”) (Compl. ¶29-34).

Functionality and Market Context

The Accused Memory Products are high-density, non-volatile storage components used in a wide array of electronic devices, from smartphones and laptops to enterprise data centers (Compl. ¶9, 28). The complaint asserts that these products are central to Micron’s business and that their sale and manufacture contribute significantly to Micron’s revenue in the United States (Compl. ¶42). The complaint positions Micron as a major player in the global 3D NAND market that is threatened by Plaintiff's innovations and market ascension (Compl. ¶8).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

10,658,378 Patent Infringement Allegations

Claim Element (from Independent Claim 15) Alleged Infringing Functionality Complaint Citation Patent Citation
a substrate with an isolation structure; The complaint alleges that the Accused Products are built upon a semiconductor substrate that includes isolation regions, a standard feature in such devices. ¶67 col. 10:1-3
an alternating conductor/dielectric layer stack disposed on the substrate; The Accused Products are alleged to be 3D NAND devices, which by definition include a vertical stack of alternating conductive and dielectric layers that form the memory cells. ¶67 col. 7:15-25
a dielectric structure on the isolation structure and extending vertically through the alternating conductor/dielectric layer stack ... wherein the dielectric structure is formed of a dielectric material; Plaintiff alleges the Accused Products contain a distinct dielectric region that extends vertically through the memory stack to facilitate the formation of through array contacts. ¶67, 71 col. 10:18-31
channel structures and slit structures extending vertically through the alternating conductor/dielectric layer stack; The Accused Products allegedly contain vertical channel structures for memory cells and slit structures for separating memory blocks, as is characteristic of 3D NAND architecture. The complaint incorporates by reference Exhibits 43-45 to show the location of these slit structures. ¶67, 68 col. 9:1-24; 9:49-55
a staircase structure disposed in the alternating conductor/dielectric layer stack; The complaint alleges the Accused Products include a staircase structure at the periphery of the memory array to allow electrical contact to the different layers of the stack. ¶67 col. 7:48-65
through array contacts (TACs) extending vertically through the dielectric and the isolation structures. Plaintiff alleges the Accused Products utilize TACs that extend through the aforementioned dielectric structure to provide vertical electrical connections. ¶67, 71 col. 10:59-62

Identified Points of Contention

  • Scope Questions: The infringement analysis for the ’378 Patent may focus on the term "dielectric structure." A key question will be whether the corresponding feature in Micron's products is a single, uniform dielectric material as described in the patent, which teaches this as a way to simplify manufacturing (col. 10:9-15), or if it is a composite or multi-layer material that might fall outside the claim scope.
  • Technical Questions: A factual question for the court will be whether the "slit structures" and "through array contacts" in the Accused Products function and are structured in the manner required by claim 15. The complaint asserts that exhibits show "precisely where the claimed slit structures can be found," suggesting this will be a point of technical, evidence-based argument (Compl. ¶68).

10,861,872 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a substrate; The Accused Products are alleged to be semiconductor devices built on a substrate. ¶89 col. 8:12-14
a memory stack including interleaved conductive layers and dielectric layers on the substrate; As 3D NAND devices, the Accused Products are alleged to contain a vertical stack of interleaved conductive and dielectric layers. ¶89 col. 8:23-28
a staircase structure on one side of the memory stack; The Accused Products allegedly include a staircase structure at the edge of the memory array to provide access to the stacked layers. ¶89 col. 8:38-41
a staircase contact in the staircase structure; The complaint alleges the Accused Products utilize contacts within the staircase structure to connect to the device's operational circuitry. ¶89 col. 2:47-51
a plurality of dummy source structures each extending vertically through the staircase structure, wherein the plurality of dummy source structures surround the staircase contact. Plaintiff alleges the Accused Products contain non-functional "dummy" structures that extend vertically through the staircase region and are arranged to surround the functional staircase contact, incorporating by reference Exhibits 49-51 to show their location. ¶89, 90 col. 6:29-37; 6:46-51

Identified Points of Contention

  • Scope Questions: The dispute over the ’872 Patent may turn on the construction of "dummy source structures" and the requirement that they "surround the staircase contact." Questions for the court may include what functional and structural characteristics define a feature as a "dummy source structure" versus another type of non-functional feature, and what geometric arrangement satisfies the term "surround" in the context of the patent's claims and figures.
  • Technical Questions: A central technical question will be whether the features identified by YMTC in Micron's chips are, in fact, non-functional structures used to improve process uniformity, as described in the patent, or if they serve another purpose. The complaint's allegation that exhibits "show precisely where the claimed dummy structures can be found" indicates this will be a point of factual dispute based on reverse engineering of the accused chips (Compl. ¶90).

V. Key Claim Terms for Construction

For the ’378 Patent:

  • The Term: "dielectric structure"
  • Context and Importance: This term is critical because the patent's asserted innovation is the formation of TACs through a simplified, single-material dielectric structure, as opposed to a complex alternating stack. Practitioners may focus on this term because infringement may depend on whether Micron's accused products contain a feature that meets this "single-material" characteristic or if it is a multi-layer structure that falls outside the claim's scope.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims define the term by its function and location: it is on the isolation structure, extends vertically through the stack, and is made of a "dielectric material" (col. 24:1-14). This language does not explicitly forbid internal sub-layers of similar dielectric materials.
    • Evidence for a Narrower Interpretation: The specification repeatedly contrasts the invention with prior art methods involving alternating layers and describes the structure as a "single-material dielectric structure" (col. 10:19). The patent’s figures, such as Figure 7, depict the dielectric structure (702) as a homogenous region, which may support a narrower construction.

For the ’872 Patent:

  • The Term: "dummy source structures"
  • Context and Importance: The patent's claims require a specific arrangement where these "dummy source structures" surround a "staircase contact." The case may turn on whether the structures accused of infringement in Micron's devices are properly classified as such. Practitioners may focus on this term because its definition—both functionally and structurally—is central to the infringement theory.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes these structures as "electrically non-functional" and serving to "provide mechanical support" (col. 6:32-34). This functional description could be argued to cover a range of non-active vertical structures.
    • Evidence for a Narrower Interpretation: Claim 1 requires that these structures "surround the staircase contact." The specific geometric arrangement shown in figures like FIG. 1A, where dummy source structures (126) are positioned around a staircase contact (122), could be used to argue that "surround" requires a specific, symmetrical, and immediately adjacent configuration that might not be present in the accused products.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendants actively induce infringement by encouraging customers, distributors, and OEMs to use the Accused Memory Products in an infringing manner. This encouragement is allegedly provided through technical materials, product specifications, and promotional literature that instruct on integrating and using the products (e.g., Compl. ¶71, 92).
  • Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. Pre-suit knowledge is alleged based on Micron citing the ’031 Patent as relevant prior art during prosecution of its own application on May 6, 2021, and a patent examiner citing the ’378 Patent against a Micron application on December 9, 2022 (Compl. ¶41). Post-suit knowledge is alleged based on the filing of the original complaint on November 9, 2023, after which Defendants allegedly continued their infringing conduct (Compl. ¶72, 93).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of claim construction and scope: can the term “dielectric structure” in the ’378 patent, which is described as a "single-material" region intended to simplify manufacturing, be construed to read on the potentially more complex vertical interconnect regions within Micron’s highly advanced 3D NAND products? Similarly, will the term "dummy source structures" in the ’872 patent be interpreted broadly based on its non-functional purpose, or narrowly based on the specific "surrounding" geometric arrangement shown in the patent's figures?
  • A key evidentiary question will be one of structural proof: beyond the pleadings, the case will depend on technical evidence from reverse engineering and discovery. Can YMTC demonstrate that the microscopic, internal architecture of Micron’s mass-produced chips contains the specific slit structures, dummy sources, and TAC regions arranged precisely as required by the asserted claims?
  • A central question for damages will be willfulness: do the alleged pre-suit citations of YMTC's patents during Micron's own R&D and patent prosecution efforts establish that Micron had knowledge of the patents and deliberately chose to engage in conduct found to be infringing, potentially justifying enhanced damages?