DCT

3:24-cv-04223

Yangtze Memory Tech Co Ltd v. Micron Technology Inc

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:24-cv-04223, N.D. Cal., 07/12/2024
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants maintain a regular and established place of business in the district, including design and product engineering facilities in San Jose and Folsom, and have committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s 3D NAND flash memory chips and DRAM products infringe eleven U.S. patents related to semiconductor device structure, fabrication methods, and operation.
  • Technical Context: The technology at issue involves high-density 3D NAND and DRAM memory, which are fundamental components for data storage in a vast range of electronic devices, from consumer products to enterprise data centers.
  • Key Procedural History: The complaint alleges that many of Plaintiff's patents are cited on the face of Defendant’s own patents, which may be used to argue that Defendant had knowledge of Plaintiff's patent portfolio.

Case Timeline

Date Event
2017-03-08 Priority Date for ’291 and ’532 Patents
2017-08-28 Priority Date for ’666, ’604, and ’838 Patents
2017-08-31 Priority Date for ’711 and ’276 Patents
2018-11-01 Priority Date for ’164 Patent
2020-02-10 Priority Date for ’941 Patent
2020-06-02 ’711 Patent Issued
2020-12-29 ’254 Patent Issued
2020-12-29 ’164 Patent Issued
2021-01-05 ’291 Patent Issued
2021-08-24 ’276 Patent Issued
2021-10-12 ’666 Patent Issued
2022-09-20 ’604 Patent Issued
2022-10-25 ’532 Patent Issued
2023-01-31 ’941 Patent Issued
2023-02-14 ’322 Patent Issued
2024-06-11 ’838 Patent Issued
2024-07-12 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

No probative visual evidence provided in complaint.

U.S. Patent No. 10,879,254 - "Three-Dimensional Memory Devices Having Through Array Contacts And Methods For Forming The Same"

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of creating vertical electrical connections, known as "through array contacts" (TACs), in 3D memory devices. Conventional methods for forming these contacts either reduce memory cell density by requiring large "barrier structures" around the contact or create manufacturing complexities that can damage the device. (’254 Patent, col. 1:23-34, col. 4:56-68).
  • The Patented Solution: The invention discloses a manufacturing method where the TAC is formed before a "slit" is created in the memory array. This slit is subsequently used for a "gate replacement" process, where sacrificial materials in the vertically stacked layers are replaced with conductive word lines. This specific sequence of forming the TAC prior to the slit is presented as a way to create a dense and reliable interconnect without the need for the space-consuming barrier structures of the prior art. (’254 Patent, Abstract; col. 2:1-7).
  • Technical Importance: This fabrication sequence aims to increase the density of 3D memory arrays and simplify the manufacturing flow, potentially leading to lower costs and higher yields for advanced memory chips. (’254 Patent, col. 5:6-14).

Key Claims at a Glance

  • The complaint asserts at least independent method claim 1 (Compl. ¶37).
  • Essential elements of Claim 1 include:
    • forming a stack comprising a plurality of dielectric/sacrificial layer pairs on a substrate;
    • forming a channel structure extending vertically through the stack;
    • forming a first opening extending vertically through the stack;
    • forming a spacer on a sidewall of the first opening;
    • forming a through array contact (TAC) extending vertically through the stack by depositing a conductor layer over the spacer in the first opening; and
    • after forming the TAC, forming a slit extending vertically through the stack.

U.S. Patent No. 11,581,322 - "Three-Dimensional Memory Devices Having Through Array Contacts And Methods For Forming The Same"

The Invention Explained

  • Problem Addressed: The ’322 Patent is a continuation of the ’254 Patent and shares an identical specification, addressing the same technical problems related to forming dense and reliable through array contacts in 3D memory devices. (’322 Patent, col. 1:23-34, col. 4:56-68).
  • The Patented Solution: The patent claims the physical structure that results from a manufacturing process like the one claimed in the ’254 Patent. It describes a 3D memory device that includes the memory stack, channel structures, TACs, and slit structures as physically embodied elements. (’322 Patent, Abstract).
  • Technical Importance: The patent protects the resulting semiconductor device itself, complementing the protection of the manufacturing method claimed in the parent ’254 Patent.

Key Claims at a Glance

  • The complaint asserts at least independent apparatus claim 1 (Compl. ¶45).
  • Essential elements of Claim 1 include:
    • a substrate;
    • a memory stack on the substrate and comprising a plurality of conductor/dielectric layer pairs;
    • a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack;
    • a through array contact (TAC) extending vertically through the conductor/dielectric layer pairs in the memory stack and buried into the substrate; and
    • a slit structure extending vertically through the conductor/dielectric layer pairs in the memory stack and configured to separate the memory stack into a plurality of memory zones.

U.S. Patent No. 10,886,291 - "Joint Opening Structures Of Three-Dimensional Memory Devices And Methods For Forming The Same"

  • Technology Synopsis: This patent addresses the difficulty of etching deep, high-aspect-ratio holes in 3D memory structures. It discloses a method for forming joint opening structures by stacking multiple independently formed channel structures on top of one another, which can improve process capability and reduce costs. (Compl. Ex. 3).
  • Asserted Claims: At least Claim 1 (Compl. ¶52).
  • Accused Features: Micron's 96L Accused Products, such as the Crucial BX500 and SSD model 1300 SATA (Compl. ¶52).

U.S. Patent No. 11,482,532 - "Joint Opening Structures of Three-Dimensional Memory Devices and Methods For Forming the Same"

  • Technology Synopsis: As a continuation of the ’291 Patent, this patent claims the resulting apparatus of the multi-level channel formation process, describing a 3D memory device with features like staircase structure dummy holes and through array contact barriers. (Compl. Ex. 4).
  • Asserted Claims: At least Claim 1 (Compl. ¶60).
  • Accused Features: Micron's 96L Accused Products, such as the Micron SSD model 1300 SATA (Compl. ¶60).

U.S. Patent No. 11,145,666 - "Staircase Structure For Memory Device"

  • Technology Synopsis: The patent describes a specific "staircase" structure at the edge of a 3D memory array, which is used to make electrical contact with the vertically stacked word lines. The invention focuses on the configuration of landing pads on the staircase steps to ensure reliable connections. (Compl. Ex. 5).
  • Asserted Claims: At least Claim 17 (Compl. ¶68).
  • Accused Features: Micron's 128L Accused Products (e.g., Micron BX500 model SSD) and 176L Accused Products (e.g., Micron SSD model 2400 PCIe) (Compl. ¶68).

U.S. Patent No. 11,450,604 - "Staircase Structure In Three-Dimensional Memory Device And Method For Forming The Same"

  • Technology Synopsis: This patent relates to staircase structures in 3D memory devices, focusing on a configuration that includes a "bridge structure" in the middle of the memory array to connect word lines. This design element relates to how the memory array is controlled and accessed. (Compl. Ex. 6).
  • Asserted Claims: At least Claim 1 (Compl. ¶75).
  • Accused Features: Micron's 232L Accused Products, such as the Micron SSD model 2250 (Compl. ¶75).

U.S. Patent No. 10,672,711 - "Word Line Contact Structure For Three-Dimensional Memory Devices And Fabrication Methods Thereof"

  • Technology Synopsis: This patent discloses structures and methods for forming word line contacts on the staircase region of a 3D memory device. The invention uses an etch-stop layer to protect underlying layers during the etching of contact openings, aiming to improve fabrication yield and reduce cost. (Compl. Ex. 7).
  • Asserted Claims: At least Claim 1 (Compl. ¶83).
  • Accused Features: Micron's 232L Accused Products, such as the Micron SSD model 2550 (Compl. ¶83).

U.S. Patent No. 11,101,276 - "Word Line Contact Structure For Three-Dimensional Memory Devices And Fabrication Methods Thereof"

  • Technology Synopsis: As a continuation of the ’711 Patent, this patent claims the resulting semiconductor device that includes the word line contact structure with a barrier layer and an etch-stop layer, as manufactured by the disclosed methods. (Compl. Ex. 8).
  • Asserted Claims: At least Claim 1 (Compl. ¶90).
  • Accused Features: Micron's 232L Accused Products, such as the Micron SSD model 2250 (Compl. ¶90).

U.S. Patent No. 11,568,941 - "Memory Including a Plurality of Portions and Used For Reducing Program Disturbance And Program Method Thereof"

  • Technology Synopsis: This patent relates to the operation of a 3D memory device, rather than its physical structure. It describes a method of applying specific voltages to word lines adjacent to a target word line during a programming operation to reduce "program disturbance," an electrical phenomenon that can cause data errors in neighboring memory cells. (Compl. Ex. 9).
  • Asserted Claims: At least Claim 1 (Compl. ¶98).
  • Accused Features: Micron's 176L Accused Products, such as the Micron SSD model 2400 PCIe Gen 4 (Compl. ¶98).

U.S. Patent No. 10,879,164 - "Integrated Circuit Electrostatic Discharge Bus Structure And Related Methods"

  • Technology Synopsis: This patent is directed to protecting integrated circuits, such as DRAM, from electrostatic discharge (ESD). It describes a bus structure layout that uses bonding wires to connect disparate groups of input/output pads to a common ESD bus, providing flexibility for irregularly shaped circuit areas. (Compl. Ex. 10).
  • Asserted Claims: At least Claim 8 (Compl. ¶106).
  • Accused Features: Micron's DRAM Accused Products, for example, the DDR5 DRAM (Compl. ¶106).

U.S. Patent No. 12,010,838 - "Staircase Structure For Memory Device"

  • Technology Synopsis: Related to the ’666 Patent family, this patent further details specific configurations of staircase structures and landing pads for memory devices, focusing on the geometry and materials of the conductive and insulating layers that form the steps. (Compl. Ex. 11).
  • Asserted Claims: At least Claim 1 (Compl. ¶114).
  • Accused Features: Micron's 128L Accused Products (e.g., Micron BX500 model SSD) and 176L Accused Products (e.g., Micron SSD model 2400 PCIe) (Compl. ¶114).

III. The Accused Instrumentality

Product Identification

The complaint identifies several generations of Defendant's memory chips, including 96-Layer, 128-Layer, 176-Layer, and 232-Layer 3D NAND memory chips, as well as DDR5 DRAM memory chips (collectively, the "Accused Memory Products") (Compl. ¶¶ 21-26). These chips are allegedly incorporated into end-user products such as Solid State Drives (SSDs) sold under Defendant's "Micron" and "Crucial" brand names (Compl. ¶¶ 27, 37, 45).

Functionality and Market Context

The accused products are high-density semiconductor memory components used for data storage in a wide range of electronic devices, including computers, mobile phones, and data centers (Compl. ¶¶ 19, 31). The complaint asserts that Defendant is a "major player in the 3D NAND space" and that its development and sales of these products have contributed to significant revenue (Compl. ¶¶ 2, 33).

IV. Analysis of Infringement Allegations

The complaint references exemplary claim charts attached as exhibits but does not provide them; therefore, the infringement theory is summarized below in prose.

’254 Patent Infringement Allegations

The complaint alleges that Defendant’s 128L, 176L, and 232L NAND products are manufactured using a process that infringes at least method claim 1 of the ’254 Patent (Compl. ¶¶ 37-38). The core of this allegation is that Defendant's fabrication process includes the specific sequence of forming a through array contact (TAC) before forming a slit used for subsequent gate replacement steps (Compl. ¶39). Infringement is alleged under 35 U.S.C. § 271(a) for acts within the U.S. and § 271(g) for the importation of products made by the patented process.

’322 Patent Infringement Allegations

The complaint alleges that Defendant’s 128L, 176L, and 232L NAND products directly infringe at least apparatus claim 1 of the ’322 Patent (Compl. ¶¶ 45-46). The allegation is that the physical memory chips themselves contain the claimed structure, which includes a memory stack with channel structures, TACs extending through the stack and into the substrate, and a slit structure that separates the memory array into zones.

Identified Points of Contention

  • Evidentiary Questions (Method Claims): For the ’254 Patent, a central dispute may be factual and evidentiary: does the Defendant’s proprietary and confidential manufacturing process practice the specific sequence of steps recited in claim 1? The allegation that the TAC is formed before the slit is a temporal limitation that will require evidence from the fabrication process itself.
  • Scope Questions (Apparatus Claims): For the ’322 Patent, the dispute may turn on claim construction and structural comparison. A key question is whether the vertical interconnects in Defendant's products meet the definition of a "through array contact (TAC)" as understood from the patent's specification, and whether the accused products contain a "slit structure" that performs the claimed function of separating the memory stack into "a plurality of memory zones."

V. Key Claim Terms for Construction

  • The Term: "through array contact (TAC)" (asserted in claim 1 of the ’254 Patent and claim 1 of the ’322 Patent)

  • Context and Importance: This term defines the central technological feature of both lead patents. Its construction will be critical for determining whether the vertical interconnect structures within Defendant’s accused products fall within the scope of the claims.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claims broadly recite a TAC as a structure "extending vertically through the... layer pairs" (’322 Patent, col. 20:3-5). The specification describes its function generally as providing "vertical interconnects between the stacked memory array device and peripheral device" (’254 Patent, col. 4:58-60).
    • Evidence for a Narrower Interpretation: The specification consistently distinguishes the invention from prior art that required "barrier structures" around the TACs to prevent manufacturing defects (’254 Patent, col. 5:4-8). Parties may argue that the term "TAC" as used in the patent implicitly excludes structures that use or are formed with such barrier structures. Further, the disclosed fabrication method, which involves forming the TAC before the slit, may be used to argue for a narrower definition tied to the resulting structure of that specific process.

  • The Term: "after forming the through array contact (TAC), forming a slit" (asserted in claim 1 of the ’254 Patent)

  • Context and Importance: This temporal limitation is the core of the asserted method claim. Infringement will depend on whether Defendant’s manufacturing process follows this claimed sequence.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party could argue that "after" simply establishes a general sequence, allowing for other unrecited manufacturing steps to occur between the formation of the TAC and the formation of the slit.
    • Evidence for a Narrower Interpretation: The patent’s Abstract and Summary of the Invention present this specific sequence as a key aspect of the solution to the technical problem (’254 Patent, Abstract; col. 2:1-7). A party may argue this language supports a construction where the slit formation must follow the TAC formation without significant deviation or in a specific relationship to the gate replacement process that uses the slit.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendant induces infringement by actively encouraging customers and distributors to use the accused products and by providing instructions and specifications (Compl. ¶28, p. 9:1-2). It also alleges contributory infringement, stating the accused memory products are essential, non-trivial components of downstream devices and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶29).
  • Willful Infringement: The complaint does not use the term "willful," but it lays the foundation for such a claim by alleging pre-suit knowledge. It asserts that Defendant "knew and knows" of Plaintiff's patents and that "Many YMTC-owned patents are cited on the face of Micron's own patents," which it claims demonstrates "Micron's knowledge of YMTC's patent portfolio" (Compl. ¶32). The prayer for relief requests a finding that the case is "exceptional" under 35 U.S.C. § 285, which can be based on findings of willful infringement or other litigation misconduct (Compl. p. 24, ¶5).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of process verification: For the asserted method patents, can Plaintiff obtain and present sufficient evidence from Defendant’s highly proprietary manufacturing lines to prove that its fabrication process maps onto the specific, sequential limitations of the claims, such as the "TAC-before-slit" step of the ’254 Patent?
  • A second key issue will be one of structural and functional definition: For the asserted apparatus patents, the case may turn on whether the physical structures and operational methods in Defendant's independently developed products can be fairly characterized as the same as those claimed in Plaintiff's patents. This raises questions such as: can Defendant’s vertical interconnect be defined as a "through array contact," and does its method of applying programming voltages constitute the "reducing program disturbance" method claimed?
  • A final question concerns knowledge and intent: Given the allegations that Defendant cited Plaintiff’s patents in its own patent prosecution, a central question for damages and attorneys' fees will be what Defendant knew about these specific patents and when. This will be critical for any potential determination of enhanced damages or a finding that the case is exceptional.