DCT

3:24-cv-06223

Renesas Electronics America Inc v. Monterey Research LLC

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:24-cv-06223, N.D. Cal., 09/03/2024
  • Venue Allegations: Plaintiff Renesas Electronics America Inc. (“REA”) alleges venue is proper because Defendant Monterey Research, LLC (“Monterey”) has its principal place of business in the Northern District of California and directed its patent enforcement activities against REA within the district.
  • Core Dispute: Plaintiff seeks a declaratory judgment that its microcontroller and System-on-Chip (SoC) products do not infringe four patents owned by Defendant related to semiconductor memory cell operation, system reset functions, and mixed-signal microcontroller architecture.
  • Technical Context: The patents-in-suit relate to foundational technologies in the semiconductor industry, governing how non-volatile memory is erased, how electronic devices manage power-on resets, and how analog and digital components are integrated on a single chip.
  • Key Procedural History: The complaint states that Monterey is a subsidiary of patent monetization firm IP Value Management and has engaged in extensive litigation against major semiconductor companies. Monterey sent letters expressly accusing REA of infringement in August 2018 and March 2022. On April 10, 2024, Monterey filed an infringement suit against REA's parent corporation and customers in the Eastern District of Texas asserting the same four patents, creating the basis for this declaratory judgment action.

Case Timeline

Date Event
2000-02-16 ’300 Patent Priority Date
2001-06-05 ’300 Patent Issue Date
2003-09-16 ’133 Patent Priority Date
2004-03-16 ’688 Patent Priority Date
2006-08-08 ’133 Patent Issue Date
2007-05-29 ’968 Patent Priority Date
2010-03-16 ’968 Patent Issue Date
2010-11-02 ’688 Patent Issue Date
2018-08-07 Monterey sends first letter to Renesas accusing infringement of ’300 and ’968 patents
2022-03-01 Monterey sends second letter to Renesas accusing infringement of ’133 and ’688 patents
2024-04-10 Monterey files suit against Renesas's parent corporation in E.D. Texas
2024-09-03 Complaint for Declaratory Judgment filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,243,300 - “Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell”

  • Patent Identification: U.S. Patent No. 6,243,300, “Substrate Hole Injection for Neutralizing Spillover Charge Generated During Programming of a Non-Volatile Memory Cell,” issued June 5, 2001 (Compl. ¶10).

The Invention Explained

  • Problem Addressed: The patent’s background describes that during the programming of multi-bit non-volatile memory cells, unwanted “spillover electrons” can become trapped in the channel, which can degrade the cell’s threshold voltage and slow down the subsequent erasure process (’300 Patent, col. 12:40-43).
  • The Patented Solution: The invention proposes a method to counteract this effect by generating “neutralizing holes” in the semiconductor substrate and injecting them into the channel to neutralize the spillover electrons (’300 Patent, Abstract). This is achieved by briefly applying a forward bias to the drain relative to the gate at the beginning of an erase cycle, a process schematically shown in Figure 6A (’300 Patent, col. 12:44-53, Fig. 6A).
  • Technical Importance: By actively clearing these unwanted charges, the patented method aims to make the memory cell erasure process faster and more reliable, addressing a key challenge in developing dense and high-performance non-volatile memory (’300 Patent, col. 13:30-36).

Key Claims at a Glance

  • The complaint does not identify specific claims but focuses on the "multi-bit" limitation (Compl. ¶26). Independent claim 1 is representative of the core method.
  • Independent Claim 1 elements:
    • A method of erasing a memory cell with a substrate that comprises a first region, a second region, a channel with spillover electrons, a gate, and a charge trapping region.
    • The method comprises generating neutralizing holes in the substrate.
    • Moving the neutralizing holes to the channel.
    • Substantially neutralizing the spillover electrons with the moved holes.
  • The complaint’s non-infringement theory appears to apply to all claims requiring a "multi-bit" memory cell structure, such as those depending from claims 7 and 8 (’300 Patent, col. 16:5-9).

U.S. Patent No. 7,679,968 - “Enhanced Erasing Operation for Non-Volatile Memory”

  • Patent Identification: U.S. Patent No. 7,679,968, “Enhanced Erasing Operation for Non-Volatile Memory,” issued March 16, 2010 (Compl. ¶11).

The Invention Explained

  • Problem Addressed: The patent’s background explains that in certain non-volatile memory cells, the erasing operation requires applying a positive voltage to the cell’s well and a negative voltage to its word line. However, parasitic capacitive coupling between the well and the word line can cause the word line voltage to rise undesirably, preventing it from reaching the necessary negative potential and thereby disrupting or delaying the erase operation (’968 Patent, col. 2:1-11).
  • The Patented Solution: The invention proposes a specific sequence of operations to avoid this problem. It applies the positive voltage to the well only after the negative voltage on the word line has already reached a stable, predetermined level (’968 Patent, Abstract). This temporal separation of the voltage applications mitigates the effect of the capacitive coupling, as illustrated in the timing diagrams of Figures 5 and 6 (’968 Patent, Fig. 5, Fig. 6; col. 4:21-29).
  • Technical Importance: This timing-based solution enables a more stable and efficient erasing process, which is critical for the performance and reliability of non-volatile memory devices used in mobile phones and digital cameras (’968 Patent, col. 1:19-22; col. 2:39-42).

Key Claims at a Glance

  • The complaint explicitly asserts non-infringement of claim 1 (Compl. ¶32).
  • Independent Claim 1 elements:
    • A semiconductor device with a memory cell array.
    • A negative voltage generating circuit for applying a negative voltage to a word line during an erasing operation.
    • A positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
    • A timing gap exists between the start of applying the negative voltage and the start of applying the positive voltage.

U.S. Patent No. 7,089,133 - “Method and Circuit for Providing a System Level Reset Function for an Electronic Device”

  • Patent Identification: U.S. Patent No. 7,089,133, “Method and Circuit for Providing a System Level Reset Function for an Electronic Device,” issued August 8, 2006 (Compl. ¶12).
  • Technology Synopsis: The patent addresses the problem of imprecise power-on-reset circuits, which can fail to hold a device in reset mode at critically low voltages, risking data corruption or damage (’133 Patent, col. 2:20-31). The invention discloses a tiered reset system that includes an initial low-precision reset, a “tunable” reset function whose precision is improved via stored calibration data, and a boot-up function to validate that data before allowing the device to operate (’133 Patent, Abstract).
  • Asserted Claims: The complaint references limitations from claim 1 (Compl. ¶38).
  • Accused Features: The complaint alleges that REA’s M16C, RA, RX, and RL series microcontrollers do not infringe because they lack "a second reset function comprising using a tunable monitor of said supply voltage" (Compl. ¶18, ¶20, ¶38).

U.S. Patent No. 7,825,688 - “Programmable Microcontroller Architecture (Mixed Analog/Digital)”

  • Patent Identification: U.S. Patent No. 7,825,688, “Programmable Microcontroller Architecture (Mixed Analog/Digital),” issued November 2, 2010 (Compl. ¶13).
  • Technology Synopsis: The patent describes a Programmable System-on-a-Chip (PSoC) architecture that integrates programmable analog and digital circuit blocks on a single chip (’688 Patent, Abstract). A key feature is a programmable interconnect structure that allows robust communication between the analog and digital domains, enabling the microcontroller's functions to be dynamically reconfigured "on-the-fly" (’688 Patent, col. 2:40-48).
  • Asserted Claims: The complaint references limitations from claim 1 (Compl. ¶44).
  • Accused Features: The complaint alleges that REA’s RH850 devices do not infringe because they do not have “a bus coupling analog input/output data and digital input/output data” for transmission between both types of circuit blocks (Compl. ¶18, ¶20, ¶44).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are various REA semiconductor products, including the RH850, M16C, RL78, H8SX, and RX series microcontrollers, as well as other products incorporating embedded flash memory (Compl. ¶17, ¶18, ¶20, ¶21).

Functionality and Market Context

  • The accused products are described as microcontrollers, analog, power, and SoC products from an industry leader (Compl. ¶2). The complaint provides specific non-infringement positions based on the technical operation of these devices. It alleges the RH850 devices use "single-bit flash EEPROM cells" (Compl. ¶26), the RX600 devices do not employ the claimed voltage application sequence during erase operations (Compl. ¶32), the RL78 devices do not perform the claimed tunable reset function (Compl. ¶38), and the RH850 devices lack a bus for transmitting both analog and digital data as claimed (Compl. ¶44). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’300 Patent Infringement Allegations

Claim Element (from Claims such as 8) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
[a memory cell comprising] a two bit memory cell REA’s RH850 devices and other accused devices are single-bit flash EEPROM cells. ¶26 col. 4:34-35
  • Identified Points of Contention:
    • Scope Questions: The primary dispute appears to be one of claim scope. Does the term "multi-bit" (or "two bit") as used in the patent’s claims read on the accused "single-bit" cells? REA's non-infringement stance suggests it does not (Compl. ¶26).
    • Technical Questions: A factual question for the court will be to determine the bit-storage architecture of the accused RH850 devices.

’968 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage The RX600 devices and other accused devices do not apply a negative voltage to a word line of the memory cell array before applying a positive voltage to a well of the memory cell array during an erasing operation. ¶32 col. 4:51-54
  • Identified Points of Contention:
    • Scope Questions: The interpretation of the term "when" will be critical. Does it require a strict temporal sequence where the negative voltage must first reach its target level before the positive voltage application begins, as REA's pleading suggests?
    • Technical Questions: What is the actual sequence of voltage applications during the erasing operation of the accused RX600 devices? This raises an evidentiary question about the operational characteristics of the accused products.

V. Key Claim Terms for Construction

  • The Term: "multi-bit flash electronically erasable programmable read only memory (EEPROM) cells" (from the '300 Patent)

  • Context and Importance: This term is central because REA’s entire stated non-infringement defense for the ’300 patent rests on the distinction between its "single-bit" cells and the allegedly claimed "multi-bit" cells (Compl. ¶26). The construction of this term may be dispositive for this patent.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent does not appear to provide explicit language supporting a construction that would read on single-bit cells. A party seeking a broader construction might focus on general statements about erasing EEPROM cells, though the context is consistently multi-bit.
    • Evidence for a Narrower Interpretation: The specification repeatedly refers to the invention in the context of a "two bit flash EEPROM cell" (’300 Patent, col. 4:34-35, col. 5:21-22). The detailed description of the preferred embodiment, including Figure 2, is explicitly directed to a two-bit symmetrical device, providing strong evidence that the invention was conceived for and is limited to multi-bit applications (’300 Patent, Fig. 2; col. 4:61-62).

  • The Term: "applying a positive voltage to a well ... when the negative voltage reaches a predetermined voltage" (from Claim 1 of the '968 Patent)

  • Context and Importance: REA's non-infringement argument for the ’968 patent is based on an alleged mismatch in the timing and sequence of operations (Compl. ¶32). The definition of "when" is therefore critical to determining if the accused products perform the claimed steps in the required order.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A party could argue "when" might encompass some temporal overlap, but the specification’s focus on solving a problem caused by simultaneous application makes this challenging.
    • Evidence for a Narrower Interpretation: The patent’s background explicitly identifies the problem as capacitive coupling that occurs when the well and word line voltages change concurrently, disrupting the erase potential (’968 Patent, col. 2:1-11). The solution is to apply the positive voltage "some time after the negative voltage is applied," delaying the coupling effect (’968 Patent, col. 2:32-34). This purpose-driven context strongly supports a sequential interpretation where "when" means "after the condition is met."

VI. Other Allegations

  • Indirect Infringement: While this is a declaratory judgment complaint, it notes that in the parallel Texas litigation, Monterey accused REA's parent company of infringement "directly and/or through subsidiaries or intermediaries," which suggests that theories of indirect infringement are part of the underlying dispute (Compl. ¶20).
  • Willful Infringement: Not alleged by REA. However, the complaint establishes a basis for a potential willfulness claim by Monterey, noting that Monterey sent express notices of infringement to REA on August 7, 2018, and March 1, 2022, establishing pre-suit knowledge of the patents-in-suit (Compl. ¶17, ¶18).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue for the ’300 patent is one of definitional scope: is the invention, which is consistently described in the context of "two bit" memory, strictly limited to "multi-bit" cells, or can the claims be construed to cover the accused "single-bit" flash EEPROM cells?
  • A key evidentiary question for the ’968, ’133, and ’688 patents will be one of factual operation: do the accused Renesas microcontrollers, as they actually function, practice the specific operational sequences and possess the specific architectural components required by the claims? For instance, does the accused erasing process for the '968 patent follow the precise temporal voltage sequence claimed, or does it operate differently?
  • For the ’688 patent, the dispute will likely focus on architectural equivalence: does the internal data bus structure of the accused RH850 devices meet the claim requirement of "a bus coupling analog input/output data and digital input/output data," raising questions about how the accused architecture compares to the integrated mixed-signal design disclosed in the patent.