DCT

4:11-cv-03139

Altera Corp v. LSI Corp

Key Events

Amended Complaint

I. Executive Summary and Procedural Information

Parties & Counsel:
- Plaintiff: Altera Corporation (Delaware)
- Defendant: LSI Corporation (California and Delaware) and Agere Systems, Inc. (Delaware)
- Plaintiff’s Counsel: Morrison & Foerster LLP
Case Identification: 4:11-cv-03139, N.D. Cal., 10/26/2011
Venue Allegations: Venue is alleged to be proper as Defendants are corporations subject to personal jurisdiction within the Northern District of California.
Core Dispute: Plaintiff alleges that Defendant’s custom and standard Integrated Circuits (“ICs”), adapters, and related systems for the storage and networking markets infringe twelve of Plaintiff's patents related to semiconductor device architecture, operation, and manufacturing.
Technical Context: The lawsuit concerns foundational technologies in programmable logic devices and high-performance integrated circuits, a highly competitive field central to the electronics industry.
Key Procedural History: This Amended Complaint was filed pursuant to a stipulation between the parties following a Covenant Not to Sue signed on October 19, 2011. The complaint also includes declaratory judgment claims alleging non-infringement and invalidity of patents owned by Defendant LSI, which the complaint states were the subject of "express assertions" by LSI against Altera prior to the litigation.

Case Timeline

Date	Event
1995-11-21	U.S. Patent No. 5,752,032 Priority Date
1996-03-13	U.S. Patent No. 5,822,553 & 5,784,649 Priority Date
1998-05-12	U.S. Patent No. 5,752,032 Issued
1998-07-21	U.S. Patent No. 5,784,649 Issued
1998-10-13	U.S. Patent No. 5,822,553 Issued
1998-11-10	U.S. Patent No. 5,834,849 Issued
2002-01-29	U.S. Patent No. 6,342,794 Issued
2004-09-28	U.S. Patent No. 6,798,302 Issued
2005-02-15	U.S. Patent No. 6,856,180 Issued
2005-02-22	U.S. Patent No. 6,859,064 Issued
2006-01-10	U.S. Patent No. 6,985,021 Issued
2006-08-15	U.S. Patent No. 7,091,613 Issued
2007-06-05	U.S. Patent No. 7,227,918 Issued
2009-06-25	Alleged earliest date of knowledge for multiple patents
2009-08-25	U.S. Patent No. RE40,883 Issued
2011-02-17	Alleged earliest date of knowledge for multiple patents
2011-10-19	Covenant Not to Sue signed between parties
2011-10-26	Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,752,032 - “Adaptive device driver using controller hardware sub-element identifier,” Issued May 12, 1998

The Invention Explained

Problem Addressed: The patent’s background describes conventional device drivers as monolithic software modules specific to a particular hardware controller and operating system (Compl. Ex. 1, ’032 Patent, col. 1:39–44). This inflexibility necessitates substantial redevelopment and testing for each new hardware version or operating system, which is described as a costly and time-consuming process (’032 Patent, col. 2:45–49).
The Patented Solution: The invention proposes a modular device driver architecture that can dynamically adapt to the specific hardware it encounters (’032 Patent, Abstract). The driver uses a "hardware sub-element identifier" read from the controller to identify the specific functional blocks (e.g., graphics controller, clock generator) present on the device (’032 Patent, col. 13:5–16). Based on this identifier, the driver dynamically loads and links the appropriate software objects needed to control those specific hardware sub-elements, creating a customized driver configuration at runtime (’032 Patent, col. 3:12–26; FIG. 2).
Technical Importance: This architecture aimed to decouple the device driver from specific hardware implementations, reducing the need for numerous, custom-written drivers and simplifying the process of supporting new hardware configurations (’032 Patent, col. 4:45–51).

Key Claims at a Glance

The complaint does not identify specific asserted claims. For the purpose of analysis, independent claim 1 is representative of the core invention.

Independent Claim 1: A controller comprising:
- a plurality of sub-elements that cooperatively operate in support of a predetermined controller function;
- a hardware identifier provided on a peripheral adapter and readable via a peripheral bus;
- said hardware identifier encoding predetermined respective specific identifications of said sub-elements, whereby an adaptively configurable device driver can specifically identify each of said sub-elements and dynamically adapt its configuration.

U.S. Patent No. 6,856,180 - “Programmable loop bandwidth in phase locked loop (PLL) circuit,” Issued February 15, 2005

The Invention Explained

Problem Addressed: The patent describes that in conventional Phase-Locked Loop (PLL) circuits, the operating bandwidth is determined by a loop filter and is constant (Compl. Ex. 2, ’180 Patent, col. 1:29–36). This fixed bandwidth is stated to limit the usefulness and operational range of the PLL circuit.
The Patented Solution: The invention is a PLL circuit with a programmable loop bandwidth, achieved through a loop filter that includes a variable resistance (’180 Patent, Abstract). By programming this resistance, typically through a set of CMOS transistors that can be switched on or off, the pole and zero of the loop filter can be shifted, thus changing the PLL's bandwidth (’180 Patent, FIG. 3; col. 6:49–55). This allows the PLL to be optimized for different operating frequencies or jitter performance requirements.
Technical Importance: This programmability allows a single PLL design to be used across a wider range of applications and operating conditions, enhancing its versatility in high-frequency integrated circuits where stability and jitter control are critical (’180 Patent, col. 2:37–43).

Key Claims at a Glance

The complaint does not identify specific asserted claims. For the purpose of analysis, independent claim 1 is representative of the core invention.

Independent Claim 1: A phase locked loop circuit comprising:
- a feedback loop; and
- a loop filter coupled to the feedback loop, wherein the loop filter is programmable in user mode to provide one of a plurality of bandwidths.

Multi-Patent Capsule: U.S. Patent No. 7,227,918

Patent Identification: 7,227,918, “Clock data recovery circuitry associated with programmable logic device circuitry,” Issued June 5, 2007 (Compl. ¶35).
Technology Synopsis: The patent describes augmenting a programmable logic device (PLD) with programmable clock data recovery (CDR) circuitry (Compl. Ex. 3, ’918 Patent, Abstract). This allows the PLD to communicate using various high-speed serial protocols where the clock signal is embedded in the data stream. The circuitry is programmable to accommodate different protocols and data rates.
Asserted Claims: Not specified in the complaint.
Accused Features: A range of LSI integrated circuits, including the Gigablaze x1, LSISAS series, MegaRAID SAS series, and Custom ASIC Logic products with SAS Link (Compl. ¶37).

Multi-Patent Capsule: U.S. Patent No. 6,798,302

Patent Identification: 6,798,302, “Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system,” Issued September 28, 2004 (Compl. ¶45).
Technology Synopsis: This patent discloses a method for implementing spread spectrum frequency modulation in a PLL using an analog approach (Compl. Ex. 4, ’302 Patent, Abstract). This technique is used to reduce electromagnetic interference (EMI) by spreading the clock signal's energy over a wider frequency band. The analog implementation provides a more flexible modulation scheme compared to purely digital methods.
Asserted Claims: Not specified in the complaint.
Accused Features: A range of LSI integrated circuits, including the Gigablaze x1, LSISAS series, MegaRAID SAS series, and Custom ASIC Logic products with SAS Link (Compl. ¶47).

Multi-Patent Capsule: U.S. Patent No. 6,985,021

Patent Identification: 6,985,021, “Circuits and techniques for conditioning differential signals,” Issued January 10, 2006 (Compl. ¶55).
Technology Synopsis: The patent describes circuitry for conditioning a differential input signal to improve its processing by a multi-standard input buffer, particularly one powered by a low voltage supply (Compl. Ex. 5, ’021 Patent, Abstract). The circuitry alters the common-mode voltage of the incoming signal to place the input buffer in a more favorable operating range, reducing propagation delays and jitter.
Asserted Claims: Not specified in the complaint.
Accused Features: A range of LSI integrated circuits, including the Gigablaze x1, LSISAS series, MegaRAID SAS series, and Custom ASIC Logic products with SAS Link (Compl. ¶57).

Multi-Patent Capsule: U.S. Patent No. 5,822,553

Patent Identification: 5,822,553, “Multiple parallel digital data stream channel controller architecture,” Issued October 13, 1998 (Compl. ¶65).
Technology Synopsis: The patent describes a channel controller architecture for managing the demand-driven transport of multiple, concurrent digital data streams in real-time (Compl. Ex. 6, ’553 Patent, Abstract). The controller is designed for use between a general-purpose processor and a special-purpose processor system, managing data segments via a segmentable buffer memory.
Asserted Claims: Not specified in the complaint.
Accused Features: StarPro 2603, 2612, and 2704 products (Compl. ¶67).

Multi-Patent Capsule: U.S. Patent No. 5,784,649

Patent Identification: 5,784,649, “Multi-threaded FIFO pool buffer and bus transfer control system,” Issued July 21, 1998 (Compl. ¶75).
Technology Synopsis: The patent discloses a bus transfer control system that manages multiple asynchronous data streams through a buffer pool comprised of a plurality of memory blocks (Compl. Ex. 7, ’649 Patent, Abstract). A transfer controller maintains status information and uses control logic to manage prioritized data transfers between various devices coupled to the buffer pool.
Asserted Claims: Not specified in the complaint.
Accused Features: StarPro 2603, 2612, and 2704 products (Compl. ¶77).

Multi-Patent Capsule: U.S. Patent No. RE40,883

Patent Identification: RE40,883, “Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision,” Issued August 25, 2009 (Compl. ¶85).
Technology Synopsis: The patent describes a reconfigurable register file that supports extended precision operations and parallel operations on lower precision data (Compl. Ex. 8, RE’883 Patent, Abstract). The register file is composed of two separate files (e.g., for even and odd registers) that can be used together to support single and double width operands efficiently.
Asserted Claims: Not specified in the complaint.
Accused Features: StarPro 2603, 2612, 2704, and 2716 products (Compl. ¶87).

Multi-Patent Capsule: U.S. Patent No. 5,834,849

Patent Identification: 5,834,849, “High density integrated circuit pad structures,” Issued November 10, 1998 (Compl. ¶95).
Technology Synopsis: The patent relates to high-density pad structures for integrated circuits (Compl. Ex. 9, ’849 Patent, Abstract). It describes forming pads on an insulating layer that overlaps the active circuitry, with connections made through holes in the layer. This structure is intended to reduce the die area occupied by pads, allowing for higher density connections suitable for technologies like flip-chip bonding.
Asserted Claims: Not specified in the complaint.
Accused Features: SAS 1078, SAS 2108, SAS 2008, B5502C20, and 3075 products (Compl. ¶97).

Multi-Patent Capsule: U.S. Patent No. 7,091,613

Patent Identification: 7,091,613, “Elongated bonding pad for wire bonding and sort probing,” Issued August 15, 2006 (Compl. ¶105).
Technology Synopsis: The patent describes an elongated bonding pad for an integrated circuit that comprises two distinct areas: a bonding area for wire bonding and an elongated probing area for wafer sort probing (Compl. Ex. 10, ’613 Patent, Abstract). This design aims to reduce the possibility of bonding wire failures caused by damage from wafer probing by separating the two functions.
Asserted Claims: Not specified in the complaint.
Accused Features: B5502C20 and Muse B2B2 HDD SOC products (Compl. ¶107).

Multi-Patent Capsule: U.S. Patent No. 6,342,794

Patent Identification: 6,342,794, “Interface for low-voltage semiconductor devices,” Issued January 29, 2002 (Compl. ¶115).
Technology Synopsis: The patent describes an interface for an integrated circuit designed to operate in a mixed-voltage environment, where the internal circuitry operates at a lower supply voltage than the external devices it interfaces with (Compl. Ex. 11, ’794 Patent, Abstract). The interface includes level-shifting and conversion circuitry to ensure compatibility between the different voltage domains.
Asserted Claims: Not specified in the complaint.
Accused Features: The ET1011 product (Compl. ¶117).

Multi-Patent Capsule: U.S. Patent No. 6,859,064

Patent Identification: 6,859,064, “Techniques for reducing leakage current in on-chip impedance termination circuits,” Issued February 22, 2005 (Compl. ¶125).
Technology Synopsis: The patent discloses techniques for reducing leakage current in on-chip impedance termination circuits used for high-speed I/O (Compl. Ex. 12, ’064 Patent, Abstract). The invention involves coupling the body of transistors in the termination circuit to a supply voltage to cut off leakage paths through drain/source-to-body diodes when the transistors are disabled.
Asserted Claims: Not specified in the complaint.
Accused Features: The ET1011 product (Compl. ¶127).

III. The Accused Instrumentality

Product Identification

The complaint accuses a wide array of products across twelve patents. These can be grouped into several categories:

General Purpose Controllers: Products such as LSIFC949X, FireStorm™, LSI MegaRAID, and 3ware Controllers are accused of infringing the ’032 Patent (Compl. ¶17).
SAS/Storage ICs: A large family of products including Gigablaze, LSISAS series controllers, MegaRAID SAS controllers, and Custom ASIC Logic products with SAS Link are accused of infringing the ’180, ’918, ’302, ’021, and ’849 Patents (Compl. ¶¶27, 37, 47, 57, 97).
Digital Signal Processors: The StarPro series of products (2603, 2612, 2704, 2716) are accused of infringing the ’553, ’649, and RE’883 Patents (Compl. ¶¶67, 77, 87).
HDD and System-on-Chip (SOC) Devices: The B5502C20 and Muse B2B2 HDD SOC products are accused of infringing the ’613 Patent (Compl. ¶107).
Ethernet Transceivers: The ET1011 product is accused of infringing the ’794 and ’064 Patents (Compl. ¶¶117, 127).

Functionality and Market Context

The complaint describes LSI and Agere as companies that develop, market, and sell custom and standard ICs, adapters, systems, and software for the storage and networking markets (Compl. ¶12).
The complaint does not provide specific technical details regarding the functionality or operation of the accused products beyond their product names and general market category.
No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint makes broad allegations of infringement (e.g., Compl. ¶¶17, 27) but does not contain specific factual allegations detailing how any feature of the accused products meets any specific claim limitation. Therefore, a claim chart cannot be constructed based on the provided complaint.

Identified Points of Contention:
- For the ’032 Patent: A central point of contention will likely be evidentiary and relate to claim scope. The primary question may be whether Altera can present evidence demonstrating that the accused controller ICs contain a "hardware identifier" that "encod[es]... specific identifications of... sub-elements" for the express purpose of dynamically adapting a device driver, as required by the claim. The dispute may focus on whether standard on-chip product ID codes or configuration registers serve this specific claimed function.
- For the ’180 Patent: The key question appears to be technical and evidentiary. A likely point of contention will be whether the Phase-Locked Loops within the accused high-speed serial controllers achieve multi-rate operation through a "programmable loop bandwidth," as claimed. The dispute may center on what technical evidence shows that the loop filter itself is "programmable" to provide a "plurality of bandwidths," versus being merely adjustable or operating in distinct, pre-set modes that may fall outside the claim's scope.

V. Key Claim Terms for Construction

Term from the ’032 Patent: "hardware sub-element identifier"

The Term: "hardware sub-element identifier"
Context and Importance: This term is central to claim 1 of the ’032 Patent and the core of the asserted invention. Its construction will likely determine whether general-purpose product identification codes or configuration registers present in the accused controllers fall within the scope of the claims. Practitioners may focus on this term because the infringement case depends on whether such common features perform the specific identifying and adapting function described in the patent.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes sub-elements as "logically independent" and distinguished by their "functional identity" (’032 Patent, col. 6:1-6). This could support a reading where any on-chip mechanism that signals the presence of a distinct functional block qualifies as the claimed identifier.
- Evidence for a Narrower Interpretation: The patent describes a specific embodiment where the identifier is read from an on-board ROM and used as a key to look up a corresponding driver file name in a "board.dat" file (’032 Patent, col. 13:49–54). This could support a narrower construction requiring a specific data structure and lookup mechanism intended for dynamic driver loading.

Term from the ’180 Patent: "programmable loop bandwidth"

The Term: "programmable loop bandwidth"
Context and Importance: This term from claim 1 of the ’180 Patent is critical because infringement will likely hinge on whether the accused PLLs meet this specific functional requirement. Defendants may argue that their circuits are merely "adjustable" for different operating modes, not that the "loop bandwidth" itself is "programmable" as the patent requires.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language recites programmability "in user mode" (’180 Patent, cl. 1), which may suggest a higher level of software-based control rather than just fixed hardware settings. The summary notes that the invention provides "independent hardware configuration options on a dynamic reconfiguration basis" (’180 Patent, col. 3:15–17), which could also support a broader view of programmability.
- Evidence for a Narrower Interpretation: The detailed description focuses on a specific circuit implementation where the "variable resistor" is formed by CMOS transistors that are turned on or off via selection signals to alter the resistance (’180 Patent, FIG. 3; col. 6:49–55). This could support a narrower construction requiring this specific type of circuit-level programmability through selectable resistive elements.

VI. Other Allegations

Indirect Infringement: For each asserted patent, the complaint alleges both inducement and contributory infringement. The inducement allegations are based on Defendants' alleged "marketing, selling, and supporting the infringing devices" (e.g., Compl. ¶19). The contributory infringement allegations assert that Defendants supplied an "important component" of the infringing products that is not a staple article of commerce and was "especially made or adapted for use in an infringing manner" (e.g., Compl. ¶20).
Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for these claims is Defendants' alleged actual knowledge of the patents as of specific dates, such as "at least February 17, 2011" for the ’032 Patent and "at least June 25, 2009" for the ’180 Patent (Compl. ¶¶18, 28). The complaint alleges that infringement subsequent to these dates of knowledge has been "willful, wanton and deliberate" (e.g., Compl. ¶¶21, 31).

VII. Analyst’s Conclusion: Key Questions for the Case

A threshold issue for the case will be one of pleading sufficiency: the complaint contains high-level infringement allegations without specific factual details mapping accused product features to claim elements. The initial phase of litigation may therefore focus on whether Altera's allegations meet the plausibility standard for patent infringement claims.
A core substantive issue will be one of definitional scope: can the term "hardware sub-element identifier," as described in the ’032 Patent in the context of a modular device driver architecture, be construed to read on the product identification or configuration registers commonly found in the accused LSI controllers?
A key evidentiary question will be one of technical operation: do the PLL circuits in the accused high-speed communication devices achieve multi-rate operation through a "programmable loop bandwidth" as claimed in the ’180 Patent, or through alternative technical means of adjustment that may fall outside the scope of the claims?