Altair Logix LLC v. Nexcom

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Nexcom USA (California)
  • Plaintiff’s Counsel: Nielsen Patents
• Case Identification: 4:19-cv-07667, N.D. Cal., 11/21/2019
• Venue Allegations: Venue is alleged to be proper based on Defendant maintaining a place of business within the Northern District of California.
• Core Dispute: Plaintiff alleges that Defendant’s digital signage players, which incorporate certain systems-on-a-chip, infringe a patent related to dynamically reconfigurable media processing circuits.
• Technical Context: The technology concerns dynamically reconfigurable processor architectures intended to provide the performance of fixed-function hardware at a lower cost by reusing computational elements for different tasks at run-time.
• Key Procedural History: The complaint notes that the asserted patent’s Claim 1 was an originally filed claim that issued without amendment and was not rejected during prosecution as anticipated by any prior art.

Case Timeline

Date	Event
1997-02-28	U.S. Patent No. 6,289,434 Priority Date
1998-02-27	U.S. Patent No. 6,289,434 Application Date
2001-09-11	U.S. Patent No. 6,289,434 Issue Date
2014-11-25	Earliest Alleged Launch of Accused Instrumentality (NDiS B114)
2019-11-21	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"

• Patent Identification: U.S. Patent No. 6,289,434 (“the ’434 Patent”), “Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates,” issued September 11, 2001.

The Invention Explained

• Problem Addressed: The patent’s background section describes a trade-off in integrated circuit design between high-performance, inflexible "fixed-function" circuits and more flexible but lower-performance or higher-cost alternatives like general-purpose microprocessors, DSPs, and FPGAs (’434 Patent, col. 1:42-2:39). Fixed-function systems suffer from "temporal redundancy," where silicon resources are dedicated to all potential functions even when not in use, increasing cost (’434 Patent, col. 2:50-57).
• The Patented Solution: The invention proposes an apparatus with multiple "media processing units" (MPUs) that can be dynamically reconfigured at run-time to perform different computational tasks (’434 Patent, col. 3:1-11). By re-using computational and storage elements in different configurations, this architecture aims to remove redundancy, reduce cost, and adapt to varying processing requirements without degrading performance, as depicted in the system architecture of Figure 3 (Compl. ¶20-21; ’434 Patent, col. 3:1-8, Fig. 3).
• Technical Importance: This architecture sought to merge the performance benefits of application-specific circuits with the flexibility of programmable processors, a central challenge in the design of System-on-Chip (SoC) devices for the growing multimedia market of its time (Compl. ¶12; ’434 Patent, col. 2:64-3:1).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 (Compl. ¶26).
• The essential elements of Claim 1 are:
  • An addressable memory for storing data and instructions.
  • A plurality of media processing units (MPUs), each coupled to the memory.
  • Each MPU comprises a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit.
  • The ALU must be capable of operating concurrently with the multiplier and arithmetic unit.
  • The bit manipulation unit must be capable of operating concurrently with the ALU and at least one of the multiplier or arithmetic unit.
  • Each MPU must be capable of performing operations simultaneously with other MPUs.
  • An "operation" is defined as receiving an instruction and data from memory, processing the data to produce a result, and providing the result to the MPU’s input/output.

III. The Accused Instrumentality

Product Identification

• The Nexcom NDiS B114 Digital Signage player (Compl. ¶26).

Functionality and Market Context

• The NDiS B114 is identified as a digital signage player powered by an ARM® Cortex®-A9 processor, specifically the Freescale (now NXP) i.MX6Quad System-on-Chip (SoC) (Compl. ¶27, ¶28, p. 11). The complaint alleges that the i.MX6Quad SoC, containing four ARM Cortex-A9 processor cores, is the infringing apparatus (Compl. ¶28). A block diagram from an NXP datasheet for the i.MX 6Quad processor is provided, highlighting sections for 'Addressable Memory,' the 'CPU Platform,' and the 'NEON per Core' unit (Compl. p. 14). The core of the infringement theory is that each ARM Cortex-A9 core, together with its integrated NEON media coprocessor, constitutes one of the claimed "media processing units" (Compl. ¶28). The product is marketed as an entry-level player for advertising and brand promotion (Compl. p. 11).

IV. Analysis of Infringement Allegations

U.S. Patent No. 6,289,434 Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs...	The memory system of the Accused Instrumentality, which is coupled to the multicore ARM processors and includes components like DDR and NAND flash memory. A diagram of the i.MX 6Quad processor shows a block labeled "Addressable Memory" (Compl. p. 14).	¶27	col. 55:23-30
a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs...	The "Quad ARM cortex A9 Core processors" within the i.MX6Quad SoC. Each core, with its NEON media coprocessor, is alleged to be a media processing unit.	¶28	col. 55:31-33
each media processing unit...comprising: a multiplier...	Each NEON media coprocessor is alleged to comprise an "Integer MUL or FP MUL" unit, as shown in a provided diagram of the NEON unit's architecture.	¶29	col. 55:34-39
an arithmetic unit...	Each NEON media coprocessor is alleged to comprise an "FP ADD" unit.	¶30	col. 55:40-45
an arithmetic logic unit...capable of operating concurrently with at least one selected from the multiplier and arithmetic unit...	Each NEON media coprocessor is alleged to comprise an "Integer ALU" that can operate concurrently with the FP MUL and FP ADD units.	¶31	col. 55:46-55
a bit manipulation unit...capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit...	Each NEON media coprocessor is alleged to comprise an "Integer Shift unit" that functions as a bit manipulation unit and can operate concurrently with the other units.	¶32	col. 55:56-56:5
each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units...	The Quad ARM Cortex-A9 core processors are alleged to be capable of performing operations on the same chip simultaneously.	¶33	col. 56:21-24
each operation comprising: receiving...an instruction and data from the memory, and processing the data...to produce at least one result...	Each ARM Cortex-A9 core with its NEON coprocessor allegedly receives instructions and data from memory, processes it, and provides a result to its input/output.	¶34	col. 56:26-33

• Identified Points of Contention:
  • Scope Questions: A primary question is whether the term "media processing unit," described in the patent as a novel, dynamically run-time reconfigurable architecture, can be construed to read on a conventional multi-core processor architecture (ARM Cortex-A9) that includes a specialized but architecturally fixed SIMD coprocessor (NEON). The complaint supports its theory with a diagram of the Cortex-A9 processor pipeline, which includes a box labeled 'Media processor' branching from the 'FPU or NEON' unit (Compl. p. 15).
  • Technical Questions: The infringement case depends on mapping the claimed functional units to specific blocks within the accused NEON coprocessor, as illustrated in a provided diagram (Compl. p. 17). This raises the question of whether the accused "Integer Shift unit" performs the full scope of functions of the "bit manipulation unit" as described in the patent. It also raises the question of whether the "FP ADD" and "Integer ALU" are sufficiently distinct to meet the separate claim limitations for an "arithmetic unit" and an "arithmetic logic unit," or if they represent a single integrated system.

V. Key Claim Terms for Construction

• The Term: "media processing unit"

  • Context and Importance: This term is the central component of the claimed invention. The outcome of the case may hinge on whether an ARM core with its NEON SIMD coprocessor falls within the scope of this term. Practitioners may focus on this term because the patent repeatedly emphasizes "run-time reconfiguring" and "re-using groups of computational and storage elements," which may suggest a different architecture than the accused product.
  • Intrinsic Evidence for a Broader Interpretation: The patent abstract states the processors can "perform arithmetic-type functions, logic functions and bit manipulation functions," a general description that could encompass the accused ARM/NEON architecture (’434 Patent, Abstract).
  • Intrinsic Evidence for a Narrower Interpretation: The specification describes the invention as an apparatus for "adaptively dynamically reconfiguring groups of computations and storage elements in run-time” (’434 Patent, col. 3:14-16). This language, along with the description of removing "temporal redundancy" by re-using elements in different configurations, may support a narrower construction limited to architectures that are fundamentally reconfigurable at a hardware level, not just executing different software instructions on fixed hardware.

• The Term: "arithmetic unit"

  • Context and Importance: Claim 1 recites both an "arithmetic unit" and an "arithmetic logic unit" as separate components of the MPU. Plaintiff must prove that the accused device contains both. A defendant may argue the terms are indistinct or that the accused device has only one integrated unit that performs both functions.
  • Intrinsic Evidence for a Broader Interpretation: The complaint alleges the "FP ADD" unit is the "arithmetic unit" and the "Integer ALU" is the "arithmetic logic unit" (Compl. ¶30-31). If the specification describes various arithmetic functions without requiring a single, monolithic "arithmetic unit," it could support the view that separate specialized blocks can meet separate claim limitations.
  • Intrinsic Evidence for a Narrower Interpretation: The patent specification describes the "Arithmetic Logic Unit (ALU)" as a 32-bit Carry-Select adder that "can also perform logical operations” (’434 Patent, col. 16:60-63). A party could argue that an ALU is, by definition, an arithmetic unit, and that the separate recitation in the claim is either redundant or refers to a structural distinction not present in the accused device.

VI. Other Allegations

The complaint does not allege indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural equivalence: Can the term "media processing unit," which is rooted in the patent’s description of a novel, run-time reconfigurable architecture, be construed to cover a conventional multi-core processor (the ARM Cortex-A9) that incorporates a specialized but architecturally fixed SIMD coprocessor (the NEON unit)?
• A key evidentiary question will be one of component distinction: Does the accused processor’s NEON media coprocessor contain both a distinct "arithmetic unit" and a distinct "arithmetic logic unit" as separately required by Claim 1, or do the alleged "FP ADD" and "Integer ALU" components constitute a single, integrated arithmetic system that fails to meet the claim’s distinct elements?