DCT
4:23-cv-03117
Bell Semiconductor, LLC v. Socionext America, Inc.
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Socionext America, Inc. (California)
- Plaintiff’s Counsel: Bush Seyferth PLLC; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 4:23-cv-03117, E.D. Mich., 08/26/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendant has committed acts of infringement in the district and maintains a regular and established place of business in Livonia, Michigan.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor design processes, used to create products like its SynQuacer SC2A11 chip, infringe patents related to efficient methods for validating circuit designs and inserting "dummy metal" during fabrication.
- Technical Context: The patents relate to electronic design automation (EDA), a field of software tools used to design complex integrated circuits, where efficiency and error-checking are critical to managing multi-million dollar manufacturing costs and schedules.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2003-10-10 | U.S. Patent No. 7,260,803 Priority Date |
| 2004-09-22 | U.S. Patent No. 7,149,989 Priority Date |
| 2006-12-12 | U.S. Patent No. 7,149,989 Issued |
| 2007-08-21 | U.S. Patent No. 7,260,803 Issued |
| 2022-08-26 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,149,989 - “Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design” (Issued Dec. 12, 2006)
The Invention Explained
- Problem Addressed: The patent addresses the inefficiency of validating integrated circuit designs. Performing a full validation check late in the design cycle is risky, as discovering a flaw can force costly and time-consuming redesigns (’989 Patent, col. 2:40-46). However, running a full check early in the process, when the design is incomplete, generates a large number of false errors, making it difficult to identify genuine problems (’989 Patent, col. 2:54-58; Compl. ¶24).
- The Patented Solution: The invention proposes a method to perform a targeted, early-stage validation. Instead of using a comprehensive rule deck, the method generates a specific, limited rule deck that includes only the rules necessary to identify "texted metal short circuits"—a specific type of critical error (’989 Patent, col. 7:17-23). By running a validation check using only this focused rule deck, designers can identify significant flaws early without the "noise" of a full validation on an incomplete design (Compl. ¶7).
- Technical Importance: This approach allows for the early detection of critical design errors related to power, ground, and signal routing, which can save significant computer processing time and prevent costly schedule delays associated with late-stage discoveries (’989 Patent, col. 3:3-11).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶26).
- Essential elements of claim 1 include:
- (a) receiving as input a representation of an integrated circuit design;
- (b) receiving as input a physical design rule deck that specifies rule checks;
- (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits between different signal sources in addition to power and ground; and
- (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify the texted metal short circuits.
- The complaint does not explicitly reserve the right to assert dependent claims but refers to infringement of "one or more claims" (Compl. ¶42).
U.S. Patent No. 7,260,803 - “Incremental Dummy Metal Insertions” (Issued Aug. 21, 2007)
The Invention Explained
- Problem Addressed: In semiconductor manufacturing, "dummy metal" is added to sparse areas of a chip to ensure the surface is uniform for the Chemical Mechanical Planarization (CMP) process (’803 Patent, col. 1:15-22). The process of calculating and inserting this dummy metal is computationally intensive and can take up to 30 hours (Compl. ¶3). The problem is that if any late-stage change is made to the circuit design (an "Engineering Change Order" or ECO), the entire dummy fill pattern is discarded and the 30-hour process must be rerun from scratch, causing significant delays and cost overruns (’803 Patent, col. 1:51-65; Compl. ¶33).
- The Patented Solution: The patent describes a more efficient, "incremental" method. After a design change is made, instead of rerunning the entire dummy fill tool, the method performs a check to see which of the pre-existing dummy metal objects now intersect with the changed design elements (’803 Patent, col. 2:9-12). It then simply deletes the conflicting dummy metal objects, leaving the vast majority of non-conflicting dummy metal in place and avoiding the need for a full, time-consuming rerun of the tool (’803 Patent, col. 2:12-14; Compl. ¶35).
- Technical Importance: This invention claims to eliminate the need for complete reruns of the dummy fill tool after each design change, saving substantial time on overall design execution and helping manufacturers meet aggressive production schedules (’803 Patent, col. 2:20-22).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶35).
- Essential elements of claim 1 include a method for performing dummy metal insertion in design data that already includes dummy metal objects, comprising:
- (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; and
- (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool.
- The complaint does not explicitly reserve the right to assert dependent claims but refers to infringement of "one or more claims" (Compl. ¶55).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the accused instrumentalities as the "Accused Processes" used by Socionext to design its semiconductor devices (Compl. ¶¶43, 56). The "SynQuacer SC2A11," a multi-core processor, is identified as a specific, exemplary product designed using these processes (Compl. ¶1, 42).
Functionality and Market Context
- The infringement allegations focus on the software-based design and validation methodologies used by Socionext, not the final hardware product itself. The complaint alleges that Socionext employs a variety of third-party EDA tools from vendors such as Cadence, Synopsys, and/or Siemens to perform its circuit design (Compl. ¶¶43, 56). These processes are alleged to include functionalities for validating circuit layouts and for inserting and managing dummy metal fill required for manufacturing (Compl. ¶¶45, 57-58). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’989 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input a representation of an integrated circuit design; | Socionext employs a design tool into which a circuit design for its SynQuacer SC2A11 is imported. | ¶43 | col. 7:10-12 |
| (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; | A design tool receives various in-design verification processes for concurrent physical design and verification. | ¶44 | col. 7:13-16 |
| (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits... | Socionext employs a design tool that includes a “short finder,” “short locator,” or similar functionality that identifies texted metal short circuits. | ¶45 | col. 7:17-23 |
| (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits... | The accused processes allow designers to select texted metal short circuits, which are shown by cell, text, net, layer and position. | ¶45 | col. 7:24-29 |
- Identified Points of Contention:
- Technical Question: The central dispute may turn on the operation of the accused "short finder" or "short locator" tools. The claim requires generating a specific rule deck that only includes rules for texted metal shorts. A key question for the court will be whether the accused tools actually generate a new, limited rule deck as a prerequisite to the check, or if they apply a broader set of rules and merely filter or highlight the output to show short circuits. The latter may not meet the claim limitation as written.
- Scope Question: The complaint's allegations for elements (c) and (d) are intertwined. A question arises as to whether merely "identifying" or "selecting" short circuits from a list (Compl. ¶45) is the same as performing the two distinct claimed steps of first "generating a specific rule deck" and then "performing a physical design validation" from that specific deck.
’803 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method for performing dummy metal insertion in design data... which includes dummy metal objects inserted by a dummy fill tool | Socionext employs a design tool that performs a dummy metal process for its SynQuacer SC2A11 layout using an "integrated" or "in-design" flow. | ¶56 | col. 5:7-9 |
| (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; | When Socionext receives an Engineering Change Order ("ECO"), it employs a design tool to perform a Design Rule Check ("DRC") to determine if there are rule violations related to metal fill geometries. | ¶57 | col. 5:9-13 |
| (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool. | Socionext uses a design tool that repairs DRC violations by allowing designers to "trim metal fill geometries that cause the short or DRC violation." | ¶58 | col. 5:14-17 |
- Identified Points of Contention:
- Scope Question: A primary point of contention will likely be the meaning of "deleting." The complaint alleges that "trimming metal fill geometries" (Compl. ¶58) satisfies this limitation. The court will need to determine whether "trimming" a portion of an object is equivalent to "deleting" the object as required by the claim, or if the claim requires removal of the entire intersecting dummy object.
- Technical Question: The claim requires "avoiding having to rerun the dummy fill tool." A question for the court will be whether the accused process of "repairing DRC violations" is functionally distinct from "rerunning the dummy fill tool," or if it is merely a localized, partial rerun of a similar fill/check/repair algorithm, which may raise questions about whether the accused process truly "avoids" a rerun in the manner contemplated by the patent.
V. Key Claim Terms for Construction
For the ’989 Patent
- The Term: "generating a specific rule deck ... that includes only physical design rules that are specific to texted metal short circuits"
- Context and Importance: This term appears to be the core of the inventive concept. Infringement will likely depend on whether the accused EDA tools perform this specific step. Practitioners may focus on this term because the allegation that a "short finder" meets this limitation suggests a potential mismatch between the claim's requirement for creating a new, limited input (a specific rule deck) and the accused tool's potential function of filtering an output.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The abstract describes a method where the "specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits," which could be argued to functionally cover any process that isolates this type of check, regardless of the precise mechanism.
- Evidence for a Narrower Interpretation: The specification discusses creating a deck with a "reduced number of design rules" to "reduce the run time" (’989 Patent, col. 5:6-12). Furthermore, the flowchart in Figure 3 explicitly depicts "GENERATE A SPECIFIC RULE DECK" (step 308) as a distinct step that occurs before "PERFORM A RULE CHECK" (step 310), which suggests the creation of a new data object, not merely the filtering of results.
For the ’803 Patent
- The Term: "deleting the intersecting dummy metal objects"
- Context and Importance: This term is the key action performed by the invention to achieve its efficiency. The plaintiff alleges that "trimming" meets this limitation, which is a likely point of dispute. Practitioners may focus on this term because the distinction between modifying an object ("trimming") and removing it entirely ("deleting") is a classic claim construction battleground.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: One could argue that from a functional perspective, removing the portion of the dummy metal that causes the intersection achieves the goal of the invention, and thus "deleting" should be interpreted to encompass any such removal, including trimming.
- Evidence for a Narrower Interpretation: The specification and figures consistently use the term "delete." The flowchart in Figure 2 shows a decision diamond for "Intersection?" that leads directly to a box labeled "Delete the object" (’803 Patent, FIG. 2, step 114). This could support a plain-meaning interpretation that the entire object identified as intersecting must be removed, not merely altered.
VI. Other Allegations
- Indirect Infringement: The complaint makes conclusory allegations of indirect infringement pursuant to 35 U.S.C. § 271, et seq. (Compl. ¶¶47, 60). However, it does not plead specific facts to support the elements of either induced or contributory infringement, such as alleging Defendant provided instructions to a third party to perform the infringing steps or supplied a component with no substantial non-infringing use.
- Willful Infringement: The complaint does not explicitly allege "willful infringement." It does allege that the infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶¶48, 61). The complaint does not allege any facts that would support a finding of willfulness, such as pre-suit knowledge of the patents via a notice letter or prior litigation.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technical operation versus claim language: For the ’989 patent, the case may turn on evidence of how the accused EDA tools actually function. Does the "short finder" feature operate by generating a new, limited rule deck before a check, as claimed, or does it apply a general rule set and then filter the output?
- A second central question will be one of definitional scope: For the ’803 patent, can the claim term "deleting" be construed to cover the accused functionality of "trimming" a portion of a metal feature? The outcome of this claim construction dispute could be dispositive for infringement of that patent.
- Finally, an evidentiary question will be one of proof: The complaint alleges infringement based on the use of proprietary design processes employing third-party software. A key challenge for the plaintiff will be to adduce sufficient evidence from discovery to demonstrate that Socionext's specific implementation and use of these general-purpose tools maps directly onto the particular steps recited in the patent claims.