DCT
4:23-cv-03118
Bell Semiconductor LLC v. Socionext America, Inc.
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Socionext America, Inc. (California)
- Plaintiff’s Counsel: BUSH SEYFERTH PLLC
- Case Identification: 4:23-cv-03118, E.D. Mich., 11/14/2022
- Venue Allegations: Venue is alleged to be proper based on Defendant maintaining a regular and established place of business in the district, specifically an office in Livonia, Michigan, and allegedly committing acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s SynQuacer SC2A11 semiconductor chips, and the design processes used to create them, infringe patents related to efficient integrated circuit (IC) design methodologies.
- Technical Context: The technology at issue addresses methods for improving the efficiency and performance of semiconductor design, specifically by localizing design revisions and by managing component density to reduce unwanted electrical effects.
- Key Procedural History: The complaint notes that the patents are part of a portfolio with a lineage tracing to Bell Labs, Lucent Technologies, Agere Systems, and LSI Corporation. No prior litigation or post-grant proceedings are mentioned.
Case Timeline
| Date | Event |
|---|---|
| 2004-11-17 | Priority Date for U.S. Patent No. 7,396,760 |
| 2004-12-17 | Priority Date for U.S. Patent No. 7,231,626 |
| 2007-06-12 | U.S. Patent No. 7,231,626 Issued |
| 2008-07-08 | U.S. Patent No. 7,396,760 Issued |
| 2022-11-14 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - "Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows" (Issued June 12, 2007)
The Invention Explained
- Problem Addressed: The patent’s background section describes the inefficiency of prior art IC design methods, where implementing even a small engineering change order (ECO) required design tools to be re-run for the entire circuit design (Compl. ¶28; ’626 Patent, col. 2:15-22). This process was time-consuming, with a typical turnaround of about one week regardless of the change's size, because the analysis time scaled with the size of the entire circuit, not the size of the change (Compl. ¶29; ’626 Patent, col. 2:37-44).
- The Patented Solution: The invention proposes a method to localize the design revision process. It involves creating a "window"—a defined area smaller than the entire circuit—that encloses the ECO changes (’626 Patent, col. 1:31-37). Subsequent design steps, like routing and verification, are performed only on the electrical nets contained within this window, leaving the rest of the design untouched (Compl. ¶4). The results from this incremental process are then merged into a copy of the original design to create a revised version, significantly reducing the time and resources needed (Compl. ¶30; ’626 Patent, col. 3:19-23).
- Technical Importance: This windowing method provided significant efficiency gains, making it less costly to implement design changes late in the development cycle and helping to shorten the overall time-to-market for complex semiconductor chips (Compl. ¶32).
Key Claims at a Glance
- The complaint asserts infringement of "one or more claims," focusing on independent Claim 1 (Compl. ¶¶ 34, 51).
- Essential elements of Claim 1 include:
- (a) receiving as input an integrated circuit design;
- (b) receiving as input an engineering change order to the integrated circuit design;
- (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window... define[s] an area that is less than an entire area of the integrated circuit design;
- (d) performing an incremental routing... only for each net... that is enclosed by the window;
- (e) replacing an area in a copy of the integrated circuit design... with results of the incremental routing to generate a revised integrated circuit design; and
- (f) generating as output the revised integrated circuit design.
U.S. Patent No. 7,396,760 - "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits" (Issued July 8, 2008)
The Invention Explained
- Problem Addressed: During semiconductor manufacturing, a process called Chemical Mechanical Planarization (CMP) requires the insertion of non-functional "dummy fill" material to ensure surface uniformity (Compl. ¶¶ 5-6). The ’760 patent explains that prior dummy fill methods focused on density requirements and only considered electrical effects within a single layer (intralayer capacitance) (Compl. ¶42; ’760 Patent, col. 1:66-2:3). This approach ignored the significant "bulk capacitance" created when dummy fill features on successive layers overlapped, which could degrade circuit timing and performance (Compl. ¶8; ’760 Patent, col. 2:3-6).
- The Patented Solution: The invention treats each consecutive pair of layers together to manage interlayer effects (’760 Patent, col. 2:7-10). The method involves determining where dummy fill features would overlap between two successive layers and then "re-arranging" the fill patterns to minimize this overlap (Compl. ¶10). This rearrangement, such as placing features in an offset or checkerboard pattern, reduces the unwanted interlayer bulk capacitance without compromising the required material density for CMP (Compl. ¶11; ’760 Patent, col. 4:28-46).
- Technical Importance: By addressing the previously unconsidered problem of interlayer capacitance from dummy fill, the invention provided a way to improve the speed and electrical performance of integrated circuits (Compl. ¶11).
Key Claims at a Glance
- The complaint asserts infringement of "one or more claims," focusing on independent Claim 1 (Compl. ¶¶ 44, 65).
- Essential elements of Claim 1 include:
- obtaining layout information of the integrated circuit... including a plurality of layers;
- obtaining a first dummy fill space for a first layer;
- obtaining a second dummy fill space for a second, successive layer;
- determining an overlap between the first and second dummy fill space; and
- minimizing the overlap by re-arranging a plurality of first and second dummy fill features.
III. The Accused Instrumentality
- Product Identification: The complaint identifies the "Socionext Accused Product" as the SynQuacer SC2A11 chip (Compl. ¶1). The infringement allegations also target the "Accused Processes," which are the circuit design methodologies used by Socionext to create the chips (Compl. ¶¶ 52, 66).
- Functionality and Market Context: The complaint alleges, on information and belief, that Socionext uses a variety of third-party electronic design automation (EDA) tools from vendors like Cadence, Synopsys, and/or Siemens (Compl. ¶¶ 52, 66). These tools are allegedly used to perform incremental routing when implementing an ECO and to arrange dummy fill in a manner that minimizes overlap between successive layers (Compl. ¶¶ 52, 66). The complaint alleges that Socionext derives "substantial revenues" from its infringing acts but does not provide specific market data for the accused products (Compl. ¶22). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
7,231,626 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (c) creating at least one window in the integrated circuit design that encloses a change ... wherein the window ... define[s] an area that is less than an entire area of the integrated circuit design | The Accused Processes allegedly define a window for the ECO to perform parasitic extraction and design rule checks only for each net within that window. | ¶53, ¶54 | col. 3:58-65 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window | Socionext's Accused Processes are alleged to perform a method for "only routing the nets affected by the ECO" by employing a design tool to perform incremental routing. | ¶52 | col. 4:5-8 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design | The Accused Processes allegedly merge the "changed area into the overall circuit layout" to generate a revised integrated circuit design. | ¶52 | col. 4:20-24 |
| (f) generating as output the revised integrated circuit design | Socionext allegedly uses its Accused Processes and design tools to generate a "revised integrated circuit design." | ¶52 | col. 1:45-46 |
- Identified Points of Contention:
- Scope Questions: A primary question may be whether the standard operation of the named third-party EDA tools (Cadence, Synopsys, Siemens) constitutes "creating at least one window" as specifically defined by the patent, or if these tools use a more general region-based modification process that falls outside the claim scope. The complaint's allegations are based on "information and belief" regarding the specific functions of these tools as used by Defendant (Compl. ¶52).
- Technical Questions: What evidence does the complaint provide that the "Accused Processes" perform routing only for nets enclosed by the window, as strictly required by the claim? The infringement analysis may focus on whether the accused routing is strictly confined to the defined window or if it affects nets outside the window, potentially creating a technical mismatch with the claim language.
7,396,760 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| obtaining layout information of the integrated circuit, the integrated circuit including a plurality of layers; | Socionext allegedly employs design tools that operate on the layout information of its Accused Product, which includes successive layers. | ¶66 | col. 3:51-57 |
| determining an overlap between the first dummy fill space and the second dummy fill space; and | The Accused Processes are alleged to "minimize the interlayer bulk capacitance after determining their overlap." | ¶66 | col. 4:25-28 |
| minimizing the overlap by re-arranging a plurality of first dummy fill features and a plurality of second dummy fill features | Socionext's tools are alleged to "rearrange dummy fill to minimize its overlap in successive layers," including the "ability to stagger the dummy fill." | ¶66 | col. 4:28-31 |
| wherein the first dummy fill space includes non-signal carrying lines ... and the second dummy fill space includes non-signal carrying lines... | The allegations concern the placement of "dummy fill," which the patent and the field define as non-signal carrying features used to meet processing requirements. | ¶66, ¶67 | col. 1:30-34 |
- Identified Points of Contention:
- Scope Questions: Does the term "minimizing the overlap by re-arranging" require a specific, deliberate algorithmic step aimed at reducing interlayer capacitance, as taught in the patent? A potential dispute is whether the accused tools perform this specific function or if any resulting overlap reduction is an incidental byproduct of a different optimization, such as achieving a target density.
- Technical Questions: Do the Accused Processes analyze layers as "consecutive pair[s]" to minimize overlap, as the patent describes (’760 Patent, col. 2:10-13)? The court may need to determine if the accused method is technically distinct, for example, by using a three-dimensional analysis that considers global, rather than pairwise, effects.
V. Key Claim Terms for Construction
'626 Patent: "window"
- Context and Importance: This term is the central pillar of the '626 patent's claims. Its construction will be critical in determining whether the functionality of the accused EDA tools falls within the scope of the claims. Practitioners may focus on this term because the infringement case depends on mapping the accused process, which is alleged on "information and belief," onto this specific claimed structure.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes a "window" as a "rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area" (’626 Patent, col. 3:59-62). This language could be argued to encompass any defined sub-region of the chip design used for a localized operation.
- Evidence for a Narrower Interpretation: Claim 1 and Figure 4 suggest the window is "bounded by coordinates" (’626 Patent, Claim 1(e), Fig. 4). This could support a narrower construction requiring a computationally defined boundary created specifically to enclose the nets affected by an ECO, as opposed to a simple user-selected area.
'760 Patent: "minimizing the overlap by re-arranging"
- Context and Importance: This phrase describes the core active step of the invention. The infringement analysis will turn on whether the accused process performs this specific, purpose-driven action.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue that any process that results in a layout with less dummy-fill overlap than a prior or alternative layout has performed "minimizing," even if that was not the primary goal of the algorithm.
- Evidence for a Narrower Interpretation: The patent describes a specific sequence: determining an overlap exists, and then taking action to "re-arrange" dummy fill features to address it, for example, by creating an offset "checkerboard pattern" (’760 Patent, col. 4:31-46, Fig. 4). This suggests "minimizing" is an intentional act to solve the specific problem of interlayer capacitance, not just a coincidental outcome. The complaint supports this by alleging an "ability to stagger the dummy fill" (Compl. ¶66).
VI. Other Allegations
- Indirect Infringement: The complaint makes general reference to 35 U.S.C. § 271, et. seq., in its infringement counts (Compl. ¶¶ 57, 70). However, it does not plead specific facts to support theories of either induced infringement (e.g., knowledge and intent to cause another to infringe) or contributory infringement. The allegations focus on Defendant's own use of the "Accused Processes" (Compl. ¶¶ 51, 65).
- Willful Infringement: The complaint does not contain an explicit count for willful infringement and does not allege that Defendant had knowledge of the patents prior to the lawsuit. The complaint alleges continuing infringement during the pendency of the patents, which may support a claim for post-filing willfulness, but no basis for pre-suit willfulness is alleged (Compl. ¶¶ 56, 69).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of evidentiary proof and definitional scope: For the '626 patent, can Plaintiff demonstrate through discovery that Defendant's use of third-party EDA tools involves the creation of a "window" and performance of "incremental routing" in the specific, constrained manner required by the claim language, or will the evidence show a more general, technically distinct process?
- A central question of causation and intent will arise for the '760 patent: Does the accused dummy fill process perform the specific, claimed step of "minimizing the overlap by re-arranging" for the purpose of reducing interlayer capacitance, or is any reduction in overlap an incidental result of an algorithm designed to optimize for other manufacturing parameters, such as pattern density?
- A key procedural question will be the extent to which allegations made "on information and belief" regarding the internal operation of Defendant's proprietary design processes are sufficient to survive early challenges and proceed to discovery, where the technical details of the "Accused Processes" can be examined.