Huang v. HFC Semiconductor Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Xiaohua Huang (Pro Se)
  • Defendant: HFC Semiconductor Corp (China)
  • Plaintiff’s Counsel: Pro Se
• Case Identification: 5:23-cv-05584, M.D. Fla., 12/04/2023
• Venue Allegations: Plaintiff alleges venue is proper because the Defendant is a foreign company, which may be sued in any judicial district.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products, including various types of memory intellectual property (IP) and chips, infringe a reissued U.S. patent related to high-speed priority encoding logic for content-addressable memory.
• Technical Context: The technology addresses methods for rapidly selecting the highest-priority result when a search in a memory system yields multiple matches, a critical function for high-performance networking and data processing hardware.
• Key Procedural History: The patent-in-suit is a reissued patent, which indicates the original patent was surrendered and re-examined by the USPTO to correct an error, potentially affecting the scope of the claims. The complaint does not mention any other prior litigation or administrative proceedings.

Case Timeline

Date	Event
2004-03-04	’259 Patent Priority Date (Provisional Application filing)
2014-11-25	’259 Patent Issue Date
2023-12-04	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Reissued Patent No. RE45,259 - "Hit Ahead Hierarchical Scalable Priority Encoding Logic and Circuits"

The Invention Explained

• Problem Addressed: In content-addressable memory (CAM), a search can result in multiple matching entries, known as a "multi-hit." The system must then execute a "priority encoding" process to select the single highest-priority match from the group. For very large memories, performing this priority calculation with conventional serial logic can be slow, creating a performance bottleneck (’259 Patent, col. 1:21-62).
• The Patented Solution: The patent describes a "multi-level hierarchical" approach to speed up priority encoding. The memory array is divided into smaller groups and levels. To avoid waiting for a full priority calculation at one level before proceeding to the next, the invention generates a preliminary "hit" signal at each level. This "Hit Ahead Priority Encoding (HAPE)" allows the next level of logic to begin its work in parallel, reducing overall delay (’259 Patent, Abstract; col. 2:1-13). This hierarchical and parallel processing architecture is depicted in Figure 2a, which shows smaller 8-entry groups (201, 202, 203) feeding into higher-level logic (206, 207).
• Technical Importance: The described method aims to improve the speed and scalability of priority encoding circuits, which are essential components for high-throughput data searching in applications like network routers and switches (’259 Patent, col. 2:3-6).

Key Claims at a Glance

• The complaint asserts independent claim 29 (’259 Patent, col. 14:49-62; Compl. ¶¶ 6-8).
• The essential elements of claim 29 are:
  • A content addressable memory (CAM) system, comprising:
  • a circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level,
  • the circuit segment configured to set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs,
  • the circuit segment output corresponding to said third logic level.
• The complaint also alleges infringement of "one or more of the claims" of the patent, reserving the right to assert other claims (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused instrumentalities broadly as "MRAM IP and chips," as well as "CAM, SRAM, eFuse and MRAM IP and chips" that have allegedly been "made and used" or "designed and used" by Defendant HFC (Compl. ¶¶ 6, 7, 11). No specific product models or part numbers are provided.

Functionality and Market Context

The complaint alleges that the accused products contain "circuit and logic" that performs the functions recited in claim 29 of the ’259 Patent (Compl. ¶¶ 7, 8). It further alleges these devices are used by Defendant at an office in Albany, NY (Compl. ¶¶ 6, 8, 11). The complaint does not provide further technical detail on the functionality or market positioning of the accused products. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references an "Exhibit X1" for a "detail analysis on how some of the accused devices infringe the claim 29" but this exhibit was not filed with the complaint (Compl. ¶8, p. 5). The infringement theory is therefore presented in conclusory narrative form. The complaint alleges that Defendant's semiconductor products contain "the circuit and logic with the function which read the claim 29" (Compl. ¶8). It does not specify which components of the accused products allegedly correspond to the "circuit segment" or how they perform the claimed functions of setting and subsequently changing a node's logic level.

• Identified Points of Contention:
  • Scope Questions: The patent is directed to "content addressable memory (CAM) system[s]." A primary question may be whether the patent's claims, specifically the term "circuit segment," can be read to cover the circuitry within the other accused memory types, such as SRAM, MRAM, and eFuse, which may operate on different principles than CAMs designed for multi-hit resolution (Compl. ¶¶ 6, 11).
  • Technical Questions: The complaint provides no factual allegations detailing how the accused products perform the specific two-step operation required by claim 29: "set a node to a second logic level... and to subsequently change the node to a third logic level." A central technical dispute will likely be whether the plaintiff can produce evidence that the accused circuits perform this specific dynamic function, as opposed to a more generic static logic operation.

V. Key Claim Terms for Construction

• The Term: "circuit segment"

• Context and Importance: This term defines the fundamental building block of the claimed invention. Its construction will determine the scope of accused hardware. Practitioners may focus on this term because the dispute will likely concern whether it is limited to the specific dynamic circuit embodiments disclosed in the patent or can be interpreted more broadly to cover any logic gate arrangement that achieves a similar result.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim language itself is functional, describing what the "circuit segment" does (generates an output, sets a node, changes a node) rather than prescribing its specific structure. This may support an interpretation covering any circuit that performs these functions.
  • Evidence for a Narrower Interpretation: The specification describes specific embodiments of the logic, such as the dynamic NOR logic of Figure 4 and the "First level hit circuit" of Figure 5, which operate via a pre-charge and subsequent discharge cycle (’259 Patent, col. 5:31-40, col. 5:41-54). A defendant may argue that the term should be limited to such dynamic logic circuits.

• The Term: "set a node... and to subsequently change the node"

• Context and Importance: This phrase describes the operational behavior of the "circuit segment." Its meaning is critical to determining whether static logic circuits, which do not typically operate on a pre-charge/discharge basis, can infringe.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: Plaintiff may argue this language does not strictly require a pre-charge and discharge cycle, but rather any two-state process where a node is initialized and then its state is changed based on inputs.
  • Evidence for a Narrower Interpretation: The detailed description of the invention’s operation consistently frames it as a two-step dynamic process. For example, it describes "pre-charge the node 503 to Vdd" and then, if an input is received, the node is discharged (’259 Patent, col. 5:31-40). This language may support a construction limiting the claim to circuits that perform this specific sequence.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement, stating that Defendant’s customers use the accused devices in an infringing manner and that the devices are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶ 12, 13). The complaint does not allege specific facts demonstrating Defendant's intent to induce infringement, such as references to instructional materials or product documentation.
• Willful Infringement: The complaint does not contain factual allegations to support pre-suit willfulness, such as a claim that Defendant knew of the ’259 Patent before the lawsuit was filed. The prayer for relief seeks enhanced damages and attorney fees, which are remedies available for willful infringement (Compl. ¶14; Prayer for Relief ¶¶ (d), (f)).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be evidentiary sufficiency: Given the complaint’s lack of specific factual allegations, can the plaintiff develop evidence through discovery to demonstrate that the accused products—spanning multiple memory technologies including CAM, SRAM, and MRAM—actually contain the specific "circuit segment" architecture that performs the dynamic, two-step logic operation required by Claim 29?
• A key legal question will be one of claim scope: Can the term "circuit segment," when read in light of the patent's specification and its description of a "set... and subsequently change" operation, be construed broadly enough to cover standard logic circuits in general-purpose memory products, or is it limited to the specific dynamic pre-charge/discharge circuits disclosed for resolving multi-hit scenarios in CAMs?