DCT

4:25-cv-09567

Concurrent Ventures LLC v. Advanced Micro Devices Inc

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 4:25-cv-09567, N.D. Cal., 12/30/2025
  • Venue Allegations: Plaintiffs allege venue is proper in the Northern District of California because Defendants maintain established places of business in the district and have committed acts of patent infringement therein. The complaint also notes that Defendants previously admitted to the appropriateness of venue in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Data Processing Unit (DPU) and SmartNIC products infringe five patents related to hardware-accelerated data processing, network optimization, and storage abstraction.
  • Technical Context: The technology concerns specialized processors (DPUs) designed to offload networking, storage, and security tasks from a computer's main CPU, a critical component in modern data centers and AI infrastructure.
  • Key Procedural History: The complaint alleges a history of pre-suit knowledge of the patented technology, citing a June 2014 meeting between Plaintiff’s agent and AMD under a non-disclosure agreement. It further alleges that a key AMD executive, Robert Hormuth, was exposed to the technology in a 2019 meeting while at his prior employer (Dell), and that his subsequent hiring by AMD and the company’s acquisition of Pensando were influenced by this knowledge. These allegations form the primary basis for the claim of willful infringement.

Case Timeline

Date Event
2013-12-06 '596 and '767 Patent Priority Date
2014-06-XX Plaintiff's agent meets with AMD under NDA
2014-12-30 '596 Patent Issued
2016-12-27 '767 Patent Issued
2018-07-15 '753, '943, and '634 Patent Priority Date
2019-XX-XX Plaintiff's agent meets with Dell, with future AMD executive Robert Hormuth in attendance
2020-12-22 '753 Patent Issued
2021-03-09 '634 Patent Issued
2021-04-20 '943 Patent Issued
Early 2022 AMD acquires Pensando Systems
2024-03-29 Original Complaint Filed
2025-12-30 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,924,596 - *"System and Method for Dividing and Synchronizing a Processing Task Across Multiple Processing Elements/Processors in Hardware"*

The Invention Explained

  • Problem Addressed: The patent’s background describes the inefficiency of synchronizing multiple processing elements to prevent the overfilling of command queues. Prior art relied on software techniques like "semaphores and mutexes," which introduced additional processing time and were considered "non-optimal" (’596 Patent, col. 1:24-29; Compl. ¶20).
  • The Patented Solution: The invention proposes a hardware-based architecture to manage this synchronization. A "second processing element" is responsible for determining when to issue a command by checking a "hardware reservation register" for available space in a command queue. If space is available, it notifies a "first processing element" to issue the command. This division of labor offloads the command-issuance decision from the main processor and uses a dedicated hardware mechanism to ensure queues are not overfilled, aiming for greater speed and efficiency. (’596 Patent, col. 3:30-4:19; Compl. ¶¶ 19-21).
  • Technical Importance: This hardware-based approach to task division and synchronization offered a potentially faster and more efficient alternative to software-based methods for managing command queues in parallel processing systems. (Compl. ¶¶ 8, 19).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and reserves the right to assert additional claims. (Compl. ¶¶ 56-57).
  • Essential elements of claim 1 include:
    • An input queue and an output queue implemented in hardware.
    • A first processing element with access to the queues.
    • At least one second processing element in communication with the first.
    • A hardware reservation register storing a value "indicative of available space" in the input queue, accessible by both processing elements.
    • Computer storage with instructions for the second processing element to: access the register, determine when the value indicates available space, and notify the first processing element to issue the command.
    • The first processing element then receives the notification, issues the command to the input queue, and receives a response from the output queue.

U.S. Patent No. 10,873,753 - *"Hardware Defined Anything In A Platform With Swappable Pods, Message Interface, Sandboxes And Memory Superposition"*

The Invention Explained

  • Problem Addressed: The patent identifies a trade-off between performance and flexibility in data processing systems. While dedicated hardware is fast, redesigning it for new applications is "an expensive proposition" and "time-consuming." Conversely, software-based systems are flexible but slower. (’753 Patent, col. 1:8-16; Compl. ¶25).
  • The Patented Solution: The invention describes a modular and reconfigurable hardware platform. The platform comprises a chassis that accepts "one or more swappable pods or cards" connected via a "module messaging interface network." These pods can contain user-definable hardware and/or software modules, allowing the system's data flow architecture to be reconfigured. The messaging network uses a specific packet header structure to address individual modules within the system, enabling complex, high-speed communication between the different hardware and software components. (’753 Patent, Abstract; col. 2:50-3:4).
  • Technical Importance: This architecture provides a framework for building powerful, reconfigurable hardware systems that can be adapted to new data processing tasks without requiring a complete redesign, aiming to combine the speed of hardware with the flexibility of software. (Compl. ¶25).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and reserves the right to assert additional claims. (Compl. ¶¶ 71-72).
  • Essential elements of claim 1 include:
    • A platform with one or more "swappable pods or cards" in a chassis, coupled through a "messaging interface network."
    • Each pod/card has hardware or software modules.
    • At least one pod/card has a portion for "user-definable" hardware or software modules.
    • The pods/cards are "user-configurable to implement data flow processing architectures."
    • A network coupled to the pods/cards supporting messaging-based communication with packets having a header that includes a chassis, board, module, instance, and type identifier for addressing.

U.S. Patent No. 10,985,943 - *"Hardware Defined Anything In A Platform With Swappable Pods, Message Interface, Sandboxes And Memory Superposition"*

  • Technology Synopsis: With a specification nearly identical to the '753 patent, this patent claims a programmable logic device (PLD) for data flow processing. The PLD has a "first region" with a hardware-based router and a "second region" with one or more "sandboxes" containing user-definable programmable circuits. A key feature is a port with a "bridge being lockable to prevent user access, and unlockable to enable user access" to the sandboxes. (Compl. ¶¶ 25, 85).
  • Asserted Claims: Independent claim 1. (Compl. ¶85).
  • Accused Features: The complaint alleges that AMD's Pensando DSCs are the claimed programmable devices. The P4 processing blocks and packet buffer constitute the "first region," while the ARM cores and other P4 components constitute the "second region" with sandboxes. AXI filters and ports between the packet buffer and P4 blocks are alleged to function as the claimed lockable bridge. (Compl. ¶¶ 87-91).

U.S. Patent No. 10,944,634 - *"Optimization for Network Connections"*

  • Technology Synopsis: The patent addresses the inefficiency of network protocols where each new connection starts without knowledge of past performance, leading to slow ramp-up times. The invention introduces a "tuner server" distinct from the network endpoints. This server collects performance data from past connections and uses it to set an optimal initial bandwidth for new connections that match a "geographical area" of a past connection, thereby shortening startup time. (Compl. ¶¶ 27-29).
  • Asserted Claims: Independent claim 8. (Compl. ¶99).
  • Accused Features: The complaint identifies the AMD SmartSwitch, which incorporates a Pensando DPU, as the "tuner server." The servers connected to the switch are the "endpoint devices." The DPU's "flow-based engine" is alleged to collect telemetry (parameter values) and use its flow state table (past network connection data) to determine bandwidth for new network flows. (Compl. ¶¶ 101-102).

U.S. Patent No. 9,529,767 - *"System And Method For Abstracting SATA And/Or SAS Storage Media Devices Via A Full Duplex Queued Command Interface…"*

  • Technology Synopsis: The patent describes a solution to the complexity and overhead of hosts managing different storage protocols like SATA and SAS. It proposes a new architecture with "master controllers" and "edge controllers" that communicate via a novel "abstraction protocol." This protocol is full-duplex and supports full command queuing, allowing the host to interact with storage devices through a simplified, unified interface while the edge controllers handle the specifics of the underlying SATA or SAS protocols. (Compl. ¶¶ 33-35).
  • Asserted Claims: Independent claim 1. (Compl. ¶111).
  • Accused Features: The complaint alleges that AMD's DPU-enabled systems create the claimed network. A host server DPU acts as the "master controller," while other DPUs (e.g., in a storage cluster) act as "edge controllers." The complaint asserts that the NVMe over Fabrics protocol, as implemented by Defendants, functions as the claimed "abstraction protocol." (Compl. ¶¶ 114-116).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are products incorporating AMD's DPU technology, including the AMD Pensando series of Data Processing Units (e.g., Giglio, Elba, Capri), Distributed Services Cards (DSC), SmartNICs, SmartSwitches, and integrated systems such as the Helios Rack. (Compl. ¶47).

Functionality and Market Context

  • The Accused Products are specialized hardware accelerators designed for data centers and high-performance computing environments. Their primary function is to offload infrastructure tasks—such as networking, storage protocols, and security services—from a server's main CPU. (Compl. ¶58). The complaint alleges these DPUs use a combination of programmable P4 data pipelines and ARM processor cores to process network and storage traffic at very high speeds. (Compl. ¶¶ 59, 74). AMD markets this technology as a "third leg of processing, alongside CPUs and GPUs," and as essential for scaling AI infrastructure by freeing up CPU and GPU resources to perform their primary computational tasks more efficiently. (Compl. ¶¶ 7, 9). The complaint includes a marketing image of an AMD Pensando DSC card, illustrating its form factor as a PCIe card intended for server integration. (Compl. p. 35).

IV. Analysis of Infringement Allegations

8,924,596 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an input queue implemented in hardware; an output queue implemented in hardware; The Accused Products contain numerous hardware queues, such as those for P4 RxDMA (input) and P4 TxDMA (output). ¶59 col. 3:30-32
a first processing element having access to said input queue and said output queue; A CPU on a host system has access to the DPU's input and output queues. ¶60 col. 3:33-35
at least one second processing element in communication with said first processing element; The processing elements on the DPU (e.g., ARM cores) are in communication with the host CPU via a PCIe interface and internal interconnects. ¶61 col. 3:36-37
a reservation register implemented in hardware storing a value indicative of available space in said input queue… The "doorbells" for the hardware queues and hardware semaphores are alleged to function as the claimed reservation registers. ¶62 col. 3:38-42
computer storage storing instructions, which when executed by said at least one second processing element: accesses said reservation register… determines when said read value indicates available space… notifies said first processing element to issue said command; The DPU's processors execute instructions to use the scheduler and access the "doorbells" or "semaphores" to determine available space, which then prompts the host CPU to issue a command. ¶63 col. 3:43-4:2
wherein said first processing element receives notification… issues said command to said input queue, and receives a response corresponding to said command from said output queue. The host CPU (first processing element) receives notification from the DPU, issues a command via the host interface to the input queue, and receives a response. ¶64 col. 4:3-7
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the claimed system of a "first" and "second" processing element, synchronized by a hardware register, can be read onto a system architecture composed of a host server CPU and a separate DPU on a PCIe card.
    • Technical Questions: The infringement theory equates the claimed "reservation register storing a value indicative of available space" with the accused "doorbells" and "hardware semaphores." A key technical question will be whether these accused mechanisms function as described in the patent—specifically, whether they are read to determine available space or if they operate differently (e.g., as write-only signaling mechanisms). The complaint provides a presentation slide illustrating the "SOC, NOC, & Hardware Queues" architecture of the accused products. (Compl. p. 25).

10,873,753 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A platform for data flow processing, comprising: one or more swappable pods or cards in one or more chassis, coupled through a messaging interface network; The AMD Pensando DSC is alleged to be the "swappable card" installed in a server "chassis," coupled via the P4 programming language and on-chip network, which functions as the "messaging interface network." ¶73 col. 12:40-44
each of the one or more swappable pods or cards having one or more hardware modules or one or more software modules; The Pensando DSC contains hardware modules (e.g., P4 pipelines) and software modules (running on ARM cores). ¶74 col. 12:45-48
one or more of the plurality of swappable pods or cards having a portion for user-definable hardware modules or user-definable software modules; The P4 pipelines are alleged to be user-definable hardware modules, and the ARM cores run user-definable software. ¶74 col. 12:49-52
the plurality of swappable pods or cards being user-configurable to implement data flow processing architectures; The accused products are designed to be configurable to implement architectures such as a SmartSwitch. ¶75 col. 12:53-55
a network coupled to the one or more swappable pods or cards and supporting messaging-based communication using packets each having a header with a chassis identifier, a board identifier, a module identifier, an instance identifier, and a type identifier… The Pensando DPUs are programmable using P4 to customize packet processing. Internal packet headers with fields like tm_iq, tm_oq, and qid are alleged to function as the claimed identifiers for routing within the device. ¶77 col. 12:56-65
  • Identified Points of Contention:
    • Scope Questions: An issue for construction may be whether a standard server with an add-in PCIe card (the DSC) constitutes the claimed "platform with swappable pods or cards in one or more chassis," or if the patent envisions a more specific, proprietary modular hardware system.
    • Technical Questions: The complaint maps the claimed header structure ("chassis identifier, board identifier, module identifier...") onto internal, intra-chip routing identifiers used within the accused DPU (qid, qtype). A technical dispute may arise over whether this intra-chip communication is equivalent to the inter-module, inter-board communication system described in the patent. The complaint includes a block diagram of the accused "Capri" DPU architecture, which may be central to this analysis. (Compl. p. 36).

V. Key Claim Terms for Construction

  • The Term: "reservation register implemented in hardware storing a value indicative of available space" (’596 Patent, Claim 1)

    • Context and Importance: This term is the lynchpin of the '596 patent's synchronization mechanism. The infringement case rests on whether the accused "doorbells" or "semaphores" meet this definition. Practitioners may focus on this term because its construction will likely determine whether the accused DPU's signaling method infringes.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the problem in general terms of avoiding queue overfills, which could support interpreting the term to cover any hardware mechanism that achieves this goal, even if the exact operation differs. The claim language requires only that the register store a "value indicative" of space, which could be argued to encompass binary states (like a semaphore) or signals (like a doorbell).
      • Evidence for a Narrower Interpretation: The abstract describes a more specific operation where the register "returns the value of the free space immediately prior to the read/reservation" and is automatically decremented. (’596 Patent, Abstract). This suggests a specific read-decrement hardware function, which may be narrower than the function of a typical doorbell (a write-based signal) or a generic semaphore (an access lock).

  • The Term: "platform for data flow processing, comprising: one or more swappable pods or cards in one or more chassis" (’753 Patent, Claim 1)

    • Context and Importance: This term defines the physical structure of the claimed invention. The dispute will center on whether a general-purpose server with a standard PCIe slot qualifies as the claimed "platform." The definition will determine if the accused products, which are often deployed as PCIe cards, are subject to the patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim uses general terms like "cards" and "chassis," which are common in the industry and could be interpreted to cover standard server components. The specification's goal is to provide a flexible architecture, which might support a broad reading that is not limited to a specific proprietary form factor. (’753 Patent, col. 2:50-55).
      • Evidence for a Narrower Interpretation: Figures 1A and 1B of the patent depict a system that appears more akin to a self-contained blade server or a custom modular chassis, where "pods" are the primary components, not merely add-in cards for a separate host computer. (’753 Patent, Figs. 1A, 1B). This may support an argument that the term requires a purpose-built modular system, not a standard server.

VI. Other Allegations

  • Indirect Infringement: For each asserted patent, the complaint alleges both induced and contributory infringement. Inducement is based on allegations that Defendants sell the Accused Products and provide documentation, user manuals, and support that instruct and encourage customers to use them in an infringing manner. (Compl. ¶¶ 67, 80, 94, 106, 122). Contributory infringement is based on the allegation that the Accused Products are a material part of the claimed inventions, are not staple articles of commerce, and have no substantial non-infringing uses. (Compl. ¶¶ 68, 81, 95, 107, 123).
  • Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. Pre-suit knowledge is alleged to stem from a June 2014 meeting between AMD and Plaintiff's agent under an NDA, and from knowledge allegedly possessed by executive Robert Hormuth from a 2019 meeting prior to his joining AMD. (Compl. ¶¶ 48-52). The complaint provides a photograph from one of these meetings, allegedly showing Mr. Hormuth. (Compl. p. 20). Post-suit knowledge is based on the filing of the original complaint on March 29, 2024. (Compl. ¶53).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical mechanism: for the ’596 patent, does an accused "doorbell" or "semaphore"—used for signaling between a host CPU and a DPU—perform the specific function of the claimed "reservation register," which the patent describes as storing and returning a value indicative of available queue space?
  • A second central issue will be one of architectural scope: for the ’753 and ’943 patents, can the claimed "platform with swappable pods" be construed to cover a standard server with an inserted PCIe card, or do the patents require a more specific, purpose-built modular hardware system as depicted in their figures?
  • A key evidentiary question will be one of pre-suit knowledge: what specific technical information was disclosed in the 2014 and 2019 meetings, and what evidence can be presented to connect that knowledge to AMD's decision to acquire Pensando and commercialize the accused DPU technology? The outcome of this question will be critical to the willfulness claim.