DCT

5:04-cv-04379

SanDisk Corp v. STMicroelectronics Inc

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:

  • Case Identification: 5:04-cv-04379, N.D. Cal., 05/22/2009

  • Venue Allegations: Venue is alleged to be proper as Defendant has committed acts of infringement in the judicial district, and a substantial part of the events giving rise to the action occurred there.

  • Core Dispute: Plaintiff alleges that Defendant’s flash memory products infringe four patents related to the architecture, programming, and verification methods for non-volatile EEPROM memory.

  • Technical Context: The technology concerns circuits and methods for reliably storing and retrieving data in flash memory, particularly multi-level cells, which are foundational components for high-density data storage in consumer electronics and enterprise systems.

  • Key Procedural History: The filing is a Third Amended Complaint in a case originally filed in 2004, suggesting a prolonged pre-trial phase or the introduction of new patents into an existing dispute.

Case Timeline

Date Event
1989-04-13 Earliest Priority Date for ’338, ’517, ’017, and ’397 Patents
1992-12-15 U.S. Patent No. 5,172,338 Issues
1999-11-23 U.S. Patent No. 5,991,517 Issues
2007-09-04 U.S. Patent No. 7,266,017 Issues
2007-10-16 U.S. Patent No. 7,283,397 Issues
2009-05-22 Third Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,172,338 - "Multi-State EEPROM Read and Write Circuits and Techniques"

  • Patent Identification: U.S. Patent No. 5,172,338, "Multi-State EEPROM Read and Write Circuits and Techniques," issued December 15, 1992.

The Invention Explained

  • Problem Addressed: The patent describes the technical challenge of reliably storing more than one bit of data per EEPROM memory cell. The threshold voltage that defines a cell's state can vary due to manufacturing processes, operating conditions, and device aging, making it difficult to accurately distinguish between multiple closely-spaced states ( ’338 Patent, col. 3:1-5).
  • The Patented Solution: The invention proposes using sets of "local reference cells" within each sector of a flash memory array. These local reference cells are subject to the same number of program/erase cycles as the data-storing cells in that sector. Because they age together, the reference cells provide an accurate, tracking benchmark for the multiple voltage thresholds needed to read multi-state data, automatically adjusting for changing conditions over the device's lifetime (Compl. ¶8; ’338 Patent, col. 3:9-24).
  • Technical Importance: This approach enabled higher-density non-volatile memory by making multi-state cell technology more reliable and commercially viable over an extended period of use (’338 Patent, col. 2:45–49).

Key Claims at a Glance

  • The complaint does not identify specific asserted claims. Independent claim 1 is representative and includes the following essential elements:
    • An integrated circuit memory system with an array of addressable EEPROM cells organized into one or more sectors.
    • Each cell has a floating gate for retaining a charge level corresponding to a memory state.
    • A reading system for determining the programmed state of a cell in a given sector.
    • The reading system comprises a set of "sector reference memory cells" associated with each sector, which are erasable with their sector and programmable to duplicate predetermined thresholds.
    • The system includes means for comparing an addressed cell's threshold to the duplicated thresholds in the associated sector reference cells.

U.S. Patent No. 5,991,517 - "Flash EEPROM System With Cell by Cell Programming Verification"

  • Patent Identification: U.S. Patent No. 5,991,517, "Flash EEPROM System With Cell by Cell Programming Verification," issued November 23, 1999.

The Invention Explained

  • Problem Addressed: When programming a group of flash memory cells in parallel, different cells will reach their target programmed state at different times. If programming pulses continue to be applied to the entire group until the slowest cell is finished, the faster cells can be over-programmed, which causes stress and reduces device reliability and endurance (’517 Patent, col. 4:6-14).
  • The Patented Solution: The invention discloses a method and system for cell-by-cell verification during a parallel programming operation. After each programming pulse, the system reads the state of each cell in the group. It then "terminates" or inhibits further programming pulses to any cell that has been correctly verified, while continuing to apply pulses to the remaining cells until they, too, reach their target state (’517 Patent, Abstract; col. 4:15-22).
  • Technical Importance: This selective, individual termination of programming enables faster parallel write operations and reduces electrical stress on the memory cells, thereby improving the overall endurance and reliability of the flash memory device (’517 Patent, col. 4:15-22).

Key Claims at a Glance

  • The complaint does not identify specific asserted claims. Independent claim 1 is representative and includes the following essential method steps:
    • Applying programming voltage conditions in parallel to a plurality of EEPROM memory cells.
    • Determining the threshold level ranges in which the individual cells lie.
    • Terminating the application of voltage conditions to individual cells that are determined to have reached their desired threshold level range.
    • Continuing to apply the voltage conditions to other cells in the plurality that have not yet reached their desired range.

U.S. Patent No. 7,266,017 - "Method for Selective Erasing and Parallel Programming/Verifying of Cell Blocks in a Flash EEPROM System"

  • Patent Identification: U.S. Patent No. 7,266,017, "Method for Selective Erasing and Parallel Programming/Verifying of Cell Blocks in a Flash EEPROM System," issued September 4, 2007 (Compl. ¶18).
  • Technology Synopsis: The patent describes a system for managing erase operations in a flash memory system. It discloses a method to select any combination of memory sectors, potentially across multiple chips, and erase them simultaneously. A key feature is the ability to de-select sectors from the group during the erase operation as they become fully erased, which prevents over-erasing and unnecessary device stress (’017 Patent, Abstract; Compl. ¶¶ 15-16).
  • Asserted Claims: The complaint does not specify asserted claims (Compl. ¶19).
  • Accused Features: The complaint accuses ST's general "semiconductors, including flash memory products" (Compl. ¶¶ 2, 3, 19).

U.S. Patent No. 7,283,397 - "Flash EEPROM System Capable of Selective Erasing and Parallel Programming/Verifying Memory Cell Blocks"

  • Patent Identification: U.S. Patent No. 7,283,397, "Flash EEPROM System Capable of Selective Erasing and Parallel Programming/Verifying Memory Cell Blocks," issued October 16, 2007 (Compl. ¶23).
  • Technology Synopsis: This patent is directed to similar subject matter as the ’017 Patent, focusing on efficient erase operations in a multi-chip flash memory system. The invention provides for selecting a combination of memory sectors for a simultaneous erase operation and, critically, de-selecting individual sectors from that operation once they are verified as erased. This prevents over-stress on cells that erase more quickly than others (’397 Patent, Abstract; Compl. ¶¶ 7-8).
  • Asserted Claims: The complaint does not specify asserted claims (Compl. ¶24).
  • Accused Features: The complaint accuses ST's general "semiconductors, including flash memory products" (Compl. ¶¶ 2, 3, 24).

III. The Accused Instrumentality

Product Identification

The complaint identifies the accused instrumentalities in general terms as "semiconductors, including flash memory products" that are designed, manufactured, marketed, and sold by Defendants STMicroelectronics, Inc. and STMicroelectronics NV (Compl. ¶¶ 2, 3).

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the functionality or market context of any specific accused product. It makes only general allegations that Defendants make and sell flash memory products (Compl. ¶¶ 2, 3). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not provide sufficient detail for an analysis of infringement allegations. The pleading asserts direct, induced, and contributory infringement for each patent-in-suit in a conclusory manner without identifying specific products or mapping any features of an accused instrumentality to the elements of the asserted patent claims (Compl. ¶¶ 9, 14, 19, 24).

V. Key Claim Terms for Construction

  • For the ’338 Patent:

    • The Term: "a set of sector reference memory cells associated with each sector"
    • Context and Importance: This term is central to the patent's proposed solution for managing threshold drift in multi-state cells. The scope of infringement will depend heavily on whether this term requires reference cells that are physically located within, and program/erase cycled with, a specific data sector, as opposed to a more generalized set of of reference cells for the entire chip. Practitioners may focus on this term because it defines the core architectural distinction from systems using only a single master reference.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim uses the general term "associated with," which could be argued to not strictly require physical co-location or simultaneous erasing, as long as a logical link exists.
      • Evidence for a Narrower Interpretation: The specification states that these cells track the main cells "closely as they are both cycled through the same number of program/erase cycles," which suggests a tight, shared operational history that may imply physical proximity and simultaneous processing (’338 Patent, col. 3:12-15).

  • For the ’517 Patent:

    • The Term: "terminating said application . . . to individual ones . . . while continuing to apply said appropriate voltage conditions to others"
    • Context and Importance: This phrase defines the core functionality of cell-by-cell program verification and inhibition. The dispute will likely center on whether the accused devices' programming algorithm performs this specific sequence of selectively stopping pulses to some cells while continuing them for other cells within the same parallel programming operation.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim language describes a functional outcome. An argument could be made that any parallel programming scheme that results in different cells receiving different numbers of programming pulses based on their state could fall within its scope.
      • Evidence for a Narrower Interpretation: The specification and figures, such as FIG. 17, describe a specific "program circuit with inhibit" for each cell path (’517 Patent, Fig. 17). This could support a narrower construction requiring a particular circuit architecture that implements this selective termination.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that ST has infringed "contributorily, and/or by inducement" for all four patents-in-suit (Compl. ¶¶ 9, 14, 19, 24). The complaint does not, however, plead any specific facts to support the elements of knowledge and intent required for such claims.

VII. Analyst’s Conclusion: Key Questions for the Case

Given the general nature of the complaint, the dispute will likely focus on fundamental technical and procedural issues before reaching detailed claim construction.

  • A primary issue will be one of architectural correspondence: Can SanDisk demonstrate that ST's accused flash memory products implement the specific "local reference cell" architecture of the ’338 patent family, where reference cells are cycled with and track the aging of specific memory sectors, as opposed to alternative industry-standard methods for managing voltage threshold drift?
  • A key question of operational equivalence will arise for the ’517 patent: Does the parallel programming algorithm in ST's products perform the claimed function of individually inhibiting programming pulses to verified cells while continuing to apply pulses to unverified cells within the same operation, or does it achieve a similar result through a fundamentally different, non-infringing method?
  • A threshold evidentiary challenge will be for SanDisk to move beyond the complaint’s general allegations and produce discovery that identifies specific accused products and maps their technical functionality to the asserted claim elements with the particularity required to sustain its infringement contentions.