DCT

5:06-cv-04496

Micron Technology Inc v. MOSAID Tech Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:06-cv-04496, N.D. Cal., 07/24/2006
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is subject to personal jurisdiction in the district, maintains two offices there, and has purposefully directed activities and has general and systematic contacts with the district.
  • Core Dispute: Plaintiff seeks a declaratory judgment that it does not infringe, and that the claims are invalid for, fourteen U.S. patents owned by Defendant related to Dynamic Random Access Memory (DRAM) circuits and technologies.
  • Technical Context: The patents relate to fundamental circuit designs for DRAM, a ubiquitous form of semiconductor memory essential for computers, servers, and other electronic devices.
  • Key Procedural History: The complaint details Defendant’s extensive litigation history against Plaintiff’s major competitors (Samsung, Hynix, Infineon), which resulted in licenses with all major DRAM suppliers except Plaintiff. Notably, Defendant recently settled with Infineon and, as part of the settlement, is seeking to vacate prior adverse claim construction and summary judgment rulings of non-infringement, which Plaintiff alleges is in preparation for litigation against it.

Case Timeline

Date Event
1990-04-06 Priority Date for "Lines Family" patents (U.S. 5,214,602 et al.)
1993-05-25 U.S. Patent No. 5214602 issues
1998-05-12 U.S. Patent No. 5,751,643 issues
1998-10-13 U.S. Patent No. 5,822,253 issues
1998-10-27 U.S. Patent No. 5,828,620 issues
2000-04-25 U.S. Patent No. 6,055,201 issues
2000-05-02 U.S. Patent No. 6,057,676 issues
2000-05-23 U.S. Patent No. 6,067,272 issues
2001-2002 MOSAID sends letters to Micron asserting infringement of DRAM patents
2001-05-22 U.S. Patent No. 6,236,581 B1 issues
2001-08-21 U.S. Patent No. 6,278,640 issues
2001-09-13 MOSAID sues Samsung for patent infringement
2002-04-09 Reissued U.S. Patent No. 37,641 issues
2002-12 Infineon files declaratory judgment action against MOSAID
2003-06-17 U.S. Patent No. 6,580,654 B2 issues
2003-08-05 U.S. Patent No. 6,603,703 B2 issues
2003-12-02 U.S. Patent No. 6,657,919 B2 issues
2005-01-18 MOSAID settles with Samsung and sues Hynix
2005-02-17 MOSAID settles with Hynix
2005-04-04 Court grants summary judgment of non-infringement for Infineon
2006-01-31 U.S. Patent No. 6,992,950 B2 issues
2006-06-14 MOSAID announces settlement with Infineon
2006-07-24 Complaint for Declaratory Judgment filed by Micron

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,214,602 - “Dynamic Memory Word Line Driver Scheme,” Issued May 25, 1993

The Invention Explained

  • Problem Addressed: In conventional DRAMs, driving a word line to a sufficiently high voltage to fully turn on a memory cell's access transistor required complex "double-boot strap" circuits. These circuits could generate excessively high voltages that adversely affect the reliability of small-geometry VLSI memories (’602 Patent, col. 1:45-54).
  • The Patented Solution: The invention provides a circuit that uses a controlled high voltage supply (Vpp) and a level shifter to directly apply this controlled voltage to the selected word line. This approach eliminates the need for double-boot-strapping, thereby avoiding excessive voltages and improving reliability (’602 Patent, col. 2:5-10; Abstract). The circuit diagram in Figure 1 illustrates a level shifter (6) and pass transistor (14A) that implement this solution.
  • Technical Importance: The solution offered a method to achieve accurate word line driving voltages, enhancing DRAM reliability, which was becoming critical as memory chip geometries shrank (’602 Patent, col. 1:50-54).

Key Claims at a Glance

  • The complaint seeks a declaratory judgment of non-infringement and invalidity as to all claims; independent claim 1 is representative of the core invention (Compl. ¶44-45).
  • Independent Claim 1:
    • A dynamic random access memory (DRAM) comprising bit lines and word lines, memory cells connected to them, each cell comprising an access field effect transistor (FET).
    • A high Vpp supply voltage source which is in excess of the high logic level voltage Vdd plus one transistor threshold voltage, but less than a transistor-damaging voltage.
    • Means for selecting the word line.
    • Means having an input driven by the selecting means for applying the Vpp supply voltage level directly to the word line through the source-drain circuit of an FET.

U.S. Patent No. 5,751,643 - “Dynamic Memory Word Line Driver,” Issued May 12, 1998

The Invention Explained

  • Problem Addressed: This patent, which is a continuation-in-part of the application leading to the ’602 Patent, addresses the same technical problem: the unreliability and complexity of double-boot-strapping circuits used to generate high word line voltages in DRAMs (’643 Patent, col. 1:43-59).
  • The Patented Solution: The solution is a word line driver circuit that incorporates a level shifter with static latching. The driver receives selection signals at a standard logic level (Vdd) and uses the latching level shifter to drive and hold control signals at a higher voltage level (Vpp). This latched, high-voltage signal is then applied directly to the word line, ensuring a stable and controlled voltage without bootstrapping (’643 Patent, col. 2:8-23). The static latching feature is described as avoiding floating high voltages and the risk of excessive leakage that could render a DRAM chip defective (’643 Patent, col. 2:36-44).
  • Technical Importance: By adding a static latching mechanism, the invention aimed to improve the stability and reduce the power leakage of the word line driver, further enhancing the reliability of high-density DRAMs (’643 Patent, col. 2:36-44).

Key Claims at a Glance

  • The complaint seeks a declaratory judgment of non-infringement and invalidity as to all claims; independent claim 1 is representative (Compl. ¶44-45).
  • Independent Claim 1:
    • A random access memory comprising word lines and dynamic memory cells.
    • A high voltage supply which supplies a controlled high voltage Vpp greater than Vdd.
    • A word line driver circuit, including a level shifter with latching, which receives word line selection signals at Vdd logic levels to drive and latch control signals at Vpp logic levels.
    • The word line driver circuit applies the controlled high voltage from the high voltage supply to a word line.

Multi-Patent Capsule: Other Patents-in-Suit

The complaint identifies twelve other patents-in-suit, grouped into several families, for which it seeks a declaration of non-infringement and invalidity (Compl. ¶40).

  • "Lines Family Patents" (U.S. 5822253; 6278640; 6603703): These patents appear to be continuations of the technology described in the ’602 and ’643 patents, concerning dynamic memory word line driver schemes (Compl. ¶40).
  • "Foss Family Patents" (U.S. 5828620; 6055201; 6236581; 6580654): The titles of these patents suggest they relate to high-voltage or boosted-voltage supplies for DRAM word lines, including charge pump and regulator circuits (Compl. ¶40).
  • "Cell Plate Family Patents" (U.S. 6057676): The title of this patent suggests it relates to regulated voltage generators for the DRAM cell plate and precharge functions (Compl. ¶40).
  • "Delayed Locked Loop Family Patents" (U.S. 6067272; 6657919; 6992950): The titles of these patents suggest they relate to delay locked loop (DLL) implementations for use in synchronous DRAMs (Compl. ¶40).
  • "Bit-Line Isolation Family Patents" (RE 37,641): The title of this reissued patent suggests it relates to DRAM architectures using imperfect isolating transistors, likely for managing bit-line sensing (Compl. ¶40).
  • Accused Features: The complaint does not specify which features of Micron's products are accused of infringing these patents, but generally alleges that MOSAID has asserted that Micron's DRAM products practice the patented technologies (Compl. ¶15).

III. The Accused Instrumentality

Product Identification

Plaintiff’s Dynamic Random Access Memory (DRAM) products (Compl. ¶11, ¶15).

Functionality and Market Context

The complaint describes Plaintiff as an industry-leading global manufacturer of DRAM devices that provide high-speed data storage and retrieval in personal computers, servers, and other products (Compl. ¶11). The complaint alleges that Plaintiff is one of four leading competitors in the DRAM industry, which together account for 75-80% of worldwide DRAM sales (Compl. ¶14). The complaint does not provide specific technical details about the operation of the accused DRAM products. Instead, it bases the existence of a controversy on Defendant's alleged assertions in 2001 and 2002 that "several of Micron's DRAM products infringed several MOSAID DRAM patents" (Compl. ¶15) and Defendant's broader public statements that "all companies that manufacture state-of-the-art DRAM products ... use MOSAID's patented circuit technology" (Compl. ¶12). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint is an action for declaratory judgment of non-infringement and does not contain affirmative infringement allegations, claim charts, or detailed technical comparisons. The basis for the asserted controversy is a series of alleged actions by Defendant, including sending letters to Plaintiff in 2001-2002 asserting infringement, suing all of Plaintiff's major competitors, and making public statements about its intent to license the entire DRAM market (Compl. ¶12, ¶15-37). The complaint alleges that Defendant’s settlement with Infineon and its subsequent effort to vacate adverse court rulings from that case confirm its intent to sue Plaintiff next (Compl. ¶33).

Identified Points of Contention

  • Jurisdictional Question: A threshold issue will be whether Defendant's course of conduct, as alleged by Plaintiff, creates an "actual and justiciable controversy" sufficient to support a declaratory judgment action, or if the action is premature.
  • Scope Questions: For the "Lines Family" patents, a central dispute would question whether the word line driver circuits within Plaintiff's DRAM products meet the structural and functional limitations of the claims. This could involve determining if Plaintiff's circuits constitute the claimed "means for applying the Vpp supply voltage level directly" or an equivalent thereof, as distinguished from the prior art double-boot-strap circuits (’602 Patent, col. 4:8-10).
  • Technical Questions: A key technical question for the "Lines Family" patents is whether Plaintiff's circuits use a "level shifter with latching" as required by claims in the ’643 patent, and whether the control signals are "set and reset by pull-down transistors gated only by Vdd level signals," a feature described as significant for avoiding boosted voltages in the driver itself (’643 Patent, col. 10:20-24).

V. Key Claim Terms for Construction

"means . . . for applying the Vpp supply voltage level directly to the word line through the source-drain circuit of an FET" (from ’602 Patent, Claim 1)

Context and Importance

This is a means-plus-function limitation under 35 U.S.C. § 112, para. 6. Its construction is critical because it defines the core mechanism distinguishing the invention from prior art "double-boot strap" circuits. The scope will be limited to the corresponding structures described in the specification and their equivalents.

Intrinsic Evidence for Interpretation

  • Evidence for a Broader Interpretation: The specification describes the function generally as applying a voltage "higher than the logic level Vdd+Vtn" without the use of bootstrapping (’602 Patent, col. 2:45-46). A party might argue that any circuit performing this function without bootstrapping is an equivalent.
  • Evidence for a Narrower Interpretation: The specification discloses a specific corresponding structure: a level shifter formed of cross-coupled P-channel transistors (7A, 7B) that drives the gate of a pass transistor (14A) connected to the Vpp source (’602 Patent, col. 2:47-66; Fig. 1). A party would argue the claim is limited to this structure and its structural, not functional, equivalents.

"a level shifter with latching" (from ’643 Patent, Claim 1)

Context and Importance

This term is central to the purported improvement of the ’643 patent over the earlier ’602 patent. The "latching" feature is described as providing stability and preventing leakage. Its definition will determine whether Plaintiff's driver circuits, which may have different stability mechanisms, fall within the claim's scope.

Intrinsic Evidence for Interpretation

  • Evidence for a Broader Interpretation: A party might argue that any circuit element that holds the level-shifted signal at a stable Vpp or Vss state qualifies as "latching." The patent notes that latching avoids "floating high voltages" (’643 Patent, col. 2:38).
  • Evidence for a Narrower Interpretation: The specification discloses a specific structure for the latch: cross-coupled field effect transistors (e.g., transistors 7A and 7B in Fig. 1) that "statically latch the level-shifted signals" (’643 Patent, col. 4:19-21). A party would argue that "latching" requires this specific cross-coupled topology or a clear structural equivalent.

VI. Other Allegations

Indirect Infringement

Plaintiff seeks a declaration that it has not "directly or indirectly infringed any claim of the patents-in-suit" (Compl. ¶45). The complaint does not, however, allege any specific facts related to indirect infringement theories that would form the basis of a controversy.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A primary procedural question will be one of justiciability: has Defendant's history of industry-wide litigation and its alleged intent to vacate adverse rulings created a controversy of "sufficient immediacy and reality" to warrant the court's jurisdiction over this declaratory judgment action?
  • A core technical issue will be one of claim scope: can the means-plus-function language in the asserted patents, which is rooted in the specific level-shifter and latching circuits disclosed, be construed to cover the diverse and potentially more advanced word line driver architectures implemented in Plaintiff's modern DRAM products?
  • A key evidentiary question will be one of invalidity: Plaintiff seeks to invalidate a broad portfolio of fourteen patents across five different technology families. The case will likely require extensive discovery and expert testimony to determine whether Plaintiff can meet its burden of proving by clear and convincing evidence that the claims of each patent are invalid over prior art not detailed in the complaint.