Nazomi Communications Inc v. Nokia Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Nazomi Communications, Inc. (Delaware)
  • Defendants: Nokia Corporation (Finland); Nokia, Inc. (Delaware); Amazon.com, Inc. (Delaware); Western Digital Corporation (Delaware); Western Digital Technologies, Inc. (Delaware); Garmin Corporation (Taiwan); Garmin International, Inc. (Kansas); Garmin USA, Inc. (Kansas); Sling Media, Inc. (Delaware); VIZIO, Inc. (California)
  • Plaintiff’s Counsel: Pepper Hamilton, LLP
• Case Identification: 5:10-cv-04686, N.D. Cal., 08/15/2011
• Venue Allegations: Venue is alleged as proper pursuant to 28 U.S.C. §§ 1391(b), 1391(c), and 1400(b).
• Core Dispute: Plaintiff alleges that Defendants’ consumer electronics products, which contain certain ARM processor cores, infringe patents related to hardware-based acceleration of Java bytecode execution.
• Technical Context: The technology involves using dedicated hardware logic to accelerate the performance of applications written in the Java programming language, which was critical for enabling complex software to run efficiently on resource-constrained mobile and embedded devices.
• Key Procedural History: The filing is a Second Amended Complaint. The complaint alleges that Defendant Nokia has had actual knowledge of the patents-in-suit since at least December 7, 2009, a fact which may be used to support claims for indirect or willful infringement.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

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U.S. Patent No. 7,080,362 - Java virtual machine hardware for RISC and CISC processors (Issued Jul. 18, 2006)

The Invention Explained

• Problem Addressed: The patent’s background section identifies the slow execution speed of Java programs as a significant disadvantage, particularly for consumer appliances Compl. ¶15 ’362 Patent, col. 1:46-53 This slowness arises because a software-based Java Virtual Machine (JVM) must interpret platform-independent "bytecodes" into processor-specific "native instructions," creating performance overhead and high power consumption ’362 Patent, col. 1:53-67
• The Patented Solution: The invention proposes implementing key parts of the JVM in dedicated hardware, described as a "Java™ hardware accelerator" ’362 Patent, col. 2:8-14 This hardware unit sits between the instruction cache and the main CPU, directly translating Java bytecodes into native instructions that the CPU can execute efficiently, thereby removing the software interpretation bottleneck ’362 Patent, Fig. 1 ’362 Patent, col. 2:59-67 The accelerator manages the Java operand stack, a core component of the JVM, within the CPU's own register file, using overflow/underflow mechanisms to interact with main memory ’362 Patent, col. 4:41-52 ’362 Patent, col. 4:53-64
• Technical Importance: This approach aimed to make the "write once, run anywhere" promise of Java feasible for mass-market, cost-sensitive devices like mobile phones and embedded systems by improving performance and reducing power consumption compared to purely software-based JVMs Compl. ¶15

Key Claims at a Glance

The complaint does not identify specific asserted claims, alleging infringement of "one or more claims" Compl. ¶31 Independent claim 1 is representative of the patent's core method:

• A method for processing instructions in a CPU capable of handling both stack-based (e.g., Java) and register-based instruction sets.
• Maintaining an "operand stack" for the stack-based instructions within a "first register file."
• Moving operands between the register file and memory using an "overflow and underflow mechanism."
• Maintaining an indication of the operand stack's depth.
• Processing both register-based and stack-based instructions in the CPU's execution unit using operands from the register file.
• Generating exceptions for selected stack-based instructions.

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U.S. Patent No. 7,225,436 - Java hardware accelerator using microcode engine (Issued May 29, 2007)

The Invention Explained

• Problem Addressed: The ’436 Patent addresses the same fundamental problem as the ’362 Patent: the performance bottleneck of software-based Java bytecode interpretation ’436 Patent, col. 1:42-53 It further addresses the architectural challenge of efficiently converting single, complex bytecodes into multiple, simpler native instructions while handling system events like interrupts ’436 Patent, abstract
• The Patented Solution: This invention discloses a hardware accelerator with a more detailed architecture, comprising a "decode stage" and a "microcode stage" ’436 Patent, abstract ’436 Patent, Fig. 8 This separation allows the decode stage to identify opportunities for instruction-level parallelism (combining multiple simple bytecodes), while the microcode stage can expand a single complex bytecode into a sequence of native instructions ’436 Patent, col. 8:35-43 The solution also introduces a "reissue buffer" that stores recently converted instructions, enabling the system to recover from a processor interrupt without having to re-translate the same bytecodes, thus improving efficiency ’436 Patent, col. 8:67-col. 9:11
• Technical Importance: By introducing a microcode-based architecture and a reissue buffer, this invention provided a more robust and sophisticated hardware design for Java acceleration, better equipped to handle the full complexity of the Java instruction set and the realities of modern operating systems.

Key Claims at a Glance

The complaint does not identify specific asserted claims, alleging infringement of "one or more claims" Compl. ¶40 Independent claim 1 is representative of the patent's core apparatus:

• A CPU for executing stack- and register-based instructions.
• Comprising an execution logic, a register file, and a "hardware accelerator."
• The hardware accelerator processes stack-based instructions by generating a new virtual machine program counter for specific "jump subroutine" ("JSR" or "JSR_W") bytecodes.
• This is achieved by sign-extending an immediate branch offset from the bytecode and adding it to the current program counter.
• The accelerator also computes and pushes a return address.

III. The Accused Instrumentality

Product Identification

• The complaint accuses a wide range of consumer electronics, including the Nokia 6350 mobile phone, Amazon Kindle 2 eReader, Western Digital My Book World Edition storage device, Garmin Nuvi 205 navigation device, Sling Media Slingbox Pro-HD video device, and VIZIO L37 and VL320M televisions Compl. ¶¶20-25

Functionality and Market Context

• The common element across all accused products is the alleged incorporation of specific processor cores—primarily the ARM1136JF-S and ARM926EJ-S—that are "capable of Java hardware acceleration" Compl. ¶¶19-25 The complaint alleges these processor cores provide the infringing functionality that allows the defendants' products to run Java applications more efficiently. These products represent a broad cross-section of the mobile and embedded electronics market where Java was a prevalent application platform Compl. ¶15

IV. Analysis of Infringement Allegations

The complaint provides a high-level, conclusory theory of infringement without mapping specific product features to claim elements. The central allegation is that the named ARM processor cores, which are capable of Java hardware acceleration, infringe the patents-in-suit (Compl. ¶¶19-27; Compl. ¶¶36). The complaint does not contain sufficient detail to construct a claim chart. No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Technical Questions: A primary question will be whether the accused ARM processors' Java acceleration technology (known commercially as Jazelle) actually operates in the manner described by the claims. For the ’362 Patent, this raises the question of whether the ARM architecture manages a Java operand stack within its general-purpose register file using an overflow/underflow mechanism as claimed. For the ’436 Patent, a key factual question is whether the processor includes a hardware accelerator that specifically handles "JSR" and "JSR_W" bytecodes by performing the claimed sign-extension and program counter calculation.
  • Scope Questions: The dispute may center on whether the architecture of the accused ARM processors falls within the scope of the patent claims. For example, for the ’362 patent, does the ARM processor's method of handling Java operations constitute "maintaining an operand stack... in a first register file," or does it use a different, non-infringing architecture, such as a dedicated hardware stack or a software-managed memory region that is merely cached?

V. Key Claim Terms for Construction

• Term: "operand stack... in a first register file" (from ’362 Patent, Claim 1)

  • Context and Importance: This term is central to the infringement analysis for the ’362 Patent. The case will likely depend on whether the accused ARM processors, when executing Java code, map the logical Java operand stack onto the physical CPU register file as required by the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent states that in one embodiment, "the Java™ CPU register file 48 substitutes for the conventional CPU register file 46," which could suggest that the term encompasses any use of the main CPU registers to hold stack data ’362 Patent, col. 4:49-51
    • Evidence for a Narrower Interpretation: The patent repeatedly distinguishes between the "conventional CPU register file 46" and a "Java™ CPU register file 48," and describes specific hardware for managing their interaction ’362 Patent, Fig. 3 ’362 Patent, col. 4:41-49 This could support a narrower construction requiring a distinct or specially-managed set of registers, not just incidental use of the conventional file.

• Term: "hardware accelerator" (from ’436 Patent, Claim 1)

  • Context and Importance: While this term appears generic, its meaning in Claim 1 is defined by the specific functions it must perform. Practitioners may focus on whether the accused ARM Jazelle technology, even if it "accelerates" Java, meets the specific functional requirements of handling "JSR" and "JSR_W" bytecodes as recited in the claim.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The summary of the invention describes the accelerator in general terms as a tool "used to translate Java™ bytecodes into native instructions for a central processing unit" ’436 Patent, col. 2:7-9
    • Evidence for a Narrower Interpretation: The claim itself ties the term to a very specific set of functions related to "JSR" instructions. The detailed description further links the accelerator to a specific architecture involving distinct decode and microcode stages, suggesting the term may be construed as being limited to hardware operating in that particular manner ’436 Patent, abstract ’436 Patent, col. 8:35-43

VI. Other Allegations

• Indirect Infringement: The complaint alleges that Nokia induces infringement by providing end users of the Nokia 6350 with user manuals containing instructions to "open and use Java applications" and to "download, install, and use Java applications" on the device Compl. ¶30 Compl. ¶39 This is alleged to constitute instructing users to perform acts that directly infringe the patents.
• Willful Infringement: The complaint does not explicitly use the term "willful," but it lays the groundwork for such a claim by alleging that Nokia has had "actual knowledge" of both the ’362 and ’436 patents since December 7, 2009 Compl. ¶29 Compl. ¶38 These allegations of pre-suit knowledge could be used to support a claim for enhanced damages for any post-knowledge infringement. The prayer for relief also requests a finding that the case is "exceptional" under 35 U.S.C. § 285 Compl., prayer d

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural congruence: Does the accused ARM Jazelle technology, the likely real-world basis for the "Java hardware acceleration" allegation, operate in a manner that maps onto the specific architectures claimed in the patents? The case may depend on whether discovery shows the ARM processors manage a Java operand stack in the CPU register file ('362 Patent) and utilize a hardware-based microcode engine for handling specific "JSR" instructions ('436 Patent), or if they employ a fundamentally different, non-infringing technical approach.
• A second key question will be one of evidentiary proof: Given the complaint’s high-level allegations, the case will hinge on Plaintiff’s ability to produce concrete evidence—likely through reverse engineering or internal documentation from ARM and the Defendants—demonstrating that the accused processors actually perform all steps of the asserted method claims and contain all elements of the asserted apparatus claims during operation. Conclusory statements about "capability" will be insufficient.