DCT

5:23-cv-04936

Huang v. Tetramem Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:23-cv-04936, N.D. Cal., 11/14/2023
  • Venue Allegations: Venue is alleged to be proper in the Northern District of California because Defendant maintains its "regular business and main office" within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s resistive random-access memory (RRAM) intellectual property (IP) and integrated circuits infringe a reissued patent related to hierarchical priority encoding logic used in memory systems.
  • Technical Context: The technology at issue involves specialized circuits designed to quickly identify the highest-priority result among multiple potential matches in a memory search, a critical function in high-speed applications like network routing.
  • Key Procedural History: The patent-in-suit is a reissued patent, which indicates the original patent claims were surrendered and re-examined by the U.S. Patent and Trademark Office. The complaint is a First Amended Complaint, and it references several exhibits (e.g., Exhibit X1) purporting to analyze infringement, though these exhibits were not filed with the complaint itself.

Case Timeline

Date Event
2004-03-04 ’RE259 Patent Priority Date
2010-01-26 Original U.S. Patent No. 7,652,903 Issues
2014-11-25 U.S. Reissued Patent No. RE45,259 Issues
2023-11-14 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Reissued Patent No. RE45,259 - Hit ahead hierarchical scalable priority encoding logic and circuits

Issued November 25, 2014. (Compl. ¶9; ’RE259 Patent, cover).

The Invention Explained

  • Problem Addressed: In certain memory types, such as ternary content-addressable memory (TCAM), a search for data can yield multiple matches, known as a "multi-hit." The system then requires a mechanism to select a single, highest-priority address from these multiple hits. Performing this "priority encoding" with conventional serial logic can be slow and inefficient, especially as the size of the memory array grows. (’RE259 Patent, col. 1:24-41, 1:59-62).
  • The Patented Solution: The patent discloses a "multi-level hierarchical" approach to solve this problem. Instead of processing all possible hits serially, the memory is divided into smaller groups or sub-blocks. Priority encoding is performed within these sub-blocks in parallel. A key aspect is "Hit Ahead Priority Encoding (HAPE)," where a simple "hit" signal is generated at each level more quickly than the full encoded address. This "hit ahead" signal is then used to accelerate the priority encoding process at the next, higher level of the hierarchy, reducing overall latency. (’RE259 Patent, Abstract; col. 2:7-12). The hierarchical structure is illustrated in Figure 2a, which shows smaller 8-entry groups (201, 202, 203) feeding into a higher-level priority block (206). (’RE259 Patent, Fig. 2a; col. 3:21-46).
  • Technical Importance: This architecture is intended to improve the speed of priority encoding while simplifying circuit implementation, making the overall memory design more flexible and scalable to larger capacities. (’RE259 Patent, col. 2:3-6).

Key Claims at a Glance

  • The complaint asserts independent claim 29. (Compl. ¶¶6, 10-11).
  • Essential elements of independent claim 29 include:
    • A content addressable memory (CAM) system, comprising:
    • a circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level,
    • the circuit segment configured to set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs,
    • the circuit segment output corresponding to said third logic level.
  • The complaint does not explicitly reserve the right to assert other claims.

III. The Accused Instrumentality

Product Identification

  • The complaint identifies "embedded RRAM IP and chips" and "ReMAM IP and chips" made by Defendant TetraMem. (Compl. ¶¶7, 10). It also references the marketing name "TetramMem's analog-RRAM- based in-memory computing technology." (Compl. ¶7).

Functionality and Market Context

  • The complaint alleges that the accused products contain "circuit and logic" for "reading and writing data and information." (Compl. ¶11). It further alleges that this functionality infringes claim 29 of the ’RE259 Patent. (Compl. ¶¶6-7). The complaint does not provide sufficient detail for analysis of the specific technical operation of the accused RRAM products. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not contain an element-by-element claim chart mapping claim limitations to the accused products. It states that an analysis is "explained in Exhibit X1," but that exhibit was not provided with the filed complaint. (Compl. ¶7).

The complaint’s narrative theory of infringement is that the accused RRAM IP and chips contain "the IC with the function which read the claim 29." (Compl. ¶7). It further alleges that the "circuit and logic design found in the ReRAM IP and chip" reads on claim 29. (Compl. ¶6). These allegations are conclusory and lack specific factual support detailing how the accused products meet each limitation of the asserted claim.

Identified Points of Contention

  • Scope Questions: A primary issue may be whether the accused "RRAM IP and chips," described as enabling "in-memory computing," fall within the scope of a "content addressable memory (CAM) system" as that term is used in the patent. (Compl. ¶7; ’RE259 Patent, cl. 29). The resolution may depend on whether the accused technology performs the search and priority-selection functions characteristic of a CAM system.
  • Technical Questions: The complaint does not explain how the accused RRAM technology performs the specific dynamic operation required by claim 29: "set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level." (’RE259 Patent, cl. 29). A central technical question will be what evidence exists that the accused products’ circuits operate in this manner, which is characteristic of certain dynamic logic families (e.g., pre-charge/discharge logic).

V. Key Claim Terms for Construction

The Term: "circuit segment"

Context and Importance

This term defines the basic building block of the claimed system. Its construction is critical because it will determine the scope of hardware structures that can infringe. The dispute may center on whether the term is limited to the specific circuit implementations shown in the patent or can be read more broadly to cover any circuit that performs the claimed functions.

Intrinsic Evidence for Interpretation

  • Evidence for a Broader Interpretation: The claim uses functional language, describing the segment as being "configured to generate" an output and "configured to set" a node, which may support a construction not limited to a specific structure. (’RE259 Patent, cl. 29).
  • Evidence for a Narrower Interpretation: The specification’s detailed description and figures disclose specific transistor-level implementations, such as dynamic NOR logic circuits, to perform the priority encoding. (’RE259 Patent, Fig. 4; col. 4:48-53). These embodiments could be cited to argue for a narrower construction limited to such circuits.

The Term: "set a node to a second logic level ... and to subsequently change the node to a third logic level"

Context and Importance

This phrase recites a specific, time-dependent electrical behavior. Infringement will depend entirely on whether the accused RRAM circuits operate according to this two-step sequence. Practitioners may focus on this term because it appears to describe a pre-charge and subsequent discharge/evaluation phase common in dynamic logic.

Intrinsic Evidence for Interpretation

  • Evidence for a Broader Interpretation: The claim language is abstract, referring to "logic levels" rather than specific voltages, which could support application to various circuit technologies. (’RE259 Patent, cl. 29).
  • Evidence for a Narrower Interpretation: The specification provides a concrete example of this operation where P-type transistors "pre-charge the node 503 to Vdd" (a high logic level), and N-type transistors later may discharge the node to ground (a low logic level) based on input signals. (’RE259 Patent, col. 5:30-41). This detailed example could be used to argue the claim requires this specific type of pre-charge/discharge mechanism.

VI. Other Allegations

Indirect Infringement

  • The complaint alleges induced infringement, stating that TetraMem induces its customers to use the accused devices. (Compl. ¶11). It asserts that the infringing uses are "not a staple article or commodity of commerce suitable for substantial non-infringing use," but provides no specific factual allegations regarding acts of inducement, such as providing instructions or manuals. (Compl. ¶¶11-12).

Willful Infringement

  • The complaint does not use the term "willful" and does not allege that Defendant had knowledge of the patent before the lawsuit was filed. It requests recovery of damages under 35 U.S.C. §284 and legal fees under §285 but does not plead a specific factual basis for willfulness or egregious conduct that would support such relief. (Compl. ¶12; Prayer for Relief (d), (f)).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "content addressable memory (CAM) system," which is rooted in the patent’s context of high-speed parallel searching and priority resolution, be construed to cover the accused "RRAM- based in-memory computing technology"?
  • A key evidentiary question will be one of technical operation: does the complaint provide, or can discovery uncover, evidence that the accused RRAM circuits perform the specific two-step, dynamic logic function required by Claim 29—setting a node to an initial state and subsequently changing it based on inputs—or is there a fundamental mismatch in how the technologies work at the circuit level?