DCT
5:24-cv-07181
Huang v. Tetramem Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Xiaohua Huang (California), pro se
- Defendant: TetraMem, Inc. (California)
- Plaintiff’s Counsel: pro se
- Case Identification: 5:24-cv-07181, N.D. Cal., 11/25/2024
- Venue Allegations: Venue is alleged to be proper based on Defendant having its regular and established place of business within the Northern District of California.
- Core Dispute: Plaintiff alleges that Defendant’s Resistive Random Access Memory (ReRAM) products infringe a patent related to priority encoding logic for Content Addressable Memory (CAM) systems.
- Technical Context: The dispute centers on integrated circuit design for memory, a critical component in high-performance computing, networking, and artificial intelligence applications.
- Key Procedural History: The complaint references a prior, withdrawn lawsuit filed by the Plaintiff against the same Defendant (Case 5:23-cv-04936-SVK). It also details an extensive history of other patent litigation initiated by the Plaintiff against different technology companies, framing the current action in the context of these past disputes. The complaint alleges pre-suit contact with Defendant’s CEO to discuss the alleged infringement.
Case Timeline
| Date | Event |
|---|---|
| 2004-03-04 | ’259 Patent Earliest Priority Date (Provisional Filing) |
| 2014-11-25 | ’259 Patent Reissue Date |
| 2020-02-01 | Plaintiff alleges meeting with Defendant's CEO |
| 2023-09-09 | Plaintiff alleges contacting Defendant's CEO re: infringement |
| 2024-11-25 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Reissue Patent No. RE45,259 - "Hit Ahead Hierarchical Scalable Priority Encoding Logic and Circuits"
The Invention Explained
- Problem Addressed: In Content Addressable Memory (CAM), a search can result in multiple matching entries, known as a "multi-hit." The process of identifying the single highest-priority match from these multiple hits can be slow, creating a performance bottleneck, particularly in large memory arrays. (’259 Patent, col. 1:22-42).
- The Patented Solution: The patent discloses a "Hit Ahead Hierarchical Scalable Priority Encoding" (HAPE) architecture. This system improves speed by generating a "hit signal" in parallel at multiple hierarchical levels of the memory array. This "hit ahead" signal allows the next level of priority encoding to begin its work without waiting for the full address from the previous level, thereby reducing overall latency and making the circuit design more scalable for larger memories. (’259 Patent, col. 2:2-14, Abstract).
- Technical Importance: This approach aimed to accelerate the performance of CAMs, which are critical components for high-speed data lookups in applications like internet routers and network switches. (Compl. ¶6).
Key Claims at a Glance
- The complaint asserts independent claim 29. (Compl. ¶22).
- The essential elements of independent claim 29 are:
- A circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level,
- the circuit segment configured to set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs,
- the circuit segment output corresponding to said third logic level.
- The complaint alleges infringement of "one or more of the claims" but focuses its technical analysis exclusively on claim 29. (Compl. ¶22).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities include Defendant's embedded ReRAM or RRAM IP, "Analog-in-ReRAM," "Memristor," "multi-level RRAM," and specific chips identified as "TetraMem MX100" and "Cullinan." (Compl. ¶15).
Functionality and Market Context
- The accused products are based on Resistive Random-Access Memory (ReRAM) technology, which uses a programmable resistor as a nonvolatile storage unit. (Compl. ¶8). The complaint alleges these products utilize a "1T1R" (one transistor, one resistor) storage cell structure, depicted in the complaint’s Figure 1. (Compl. ¶16).
- The core of the infringement allegation focuses on the "read circuit" used to access the data stored in the ReRAM cell array. (Compl. p. 12, Fig. 3). The complaint presents a schematic of the accused read circuit, which it alleges is turned 90 degrees from a standard column in the ReRAM array shown in Figure 2. (Compl. ¶17-18).
- The complaint alleges that Defendant markets these ReRAM products for use in Artificial Intelligence (AI) and in-memory computing applications. (Compl. ¶8).
IV. Analysis of Infringement Allegations
RE45,259 Infringement Allegations
| Claim Element (from Independent Claim 29) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A content addressable memory (CAM) system, comprising: (1) a circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level, | The complaint alleges the read circuit of Defendant's ReRAM, shown in Figure 3, performs this function. The "plurality of circuit segment inputs" are the word lines (WL0, WL1,...), and a change in their voltage level generates an output voltage. (Compl. p. 12, Fig. 3). | ¶(1) on p. 14 | col. 10:49-56 |
| (2) the circuit segment configured to set a node to a second logic level in response to an input signal, and | This is mapped to "Step 1" of the accused read operation. The "input signal" is the read enable signal "Ren," which turns on a transistor, setting the node "Vx" to an initial voltage "V0." (Compl. p. 12, Fig. 3). | ¶(2) on p. 14 | col. 10:57-61 |
| (3) to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs, the circuit segment output corresponding to said third logic level. | This is mapped to "Step 2" of the read operation. A word line (e.g., WL0) is activated while the "Ren" signal is deactivated. This connects the memory cell's resistor to the node "Vx," changing its voltage from V0 to a new level (V1, V2, etc.) that corresponds to the stored resistance value. This new voltage is the circuit output. (Compl. p. 12, Fig. 3). | ¶(3) on p. 15 | col. 10:61-63 |
- Identified Points of Contention:
- Scope Questions: A primary issue may be whether the preamble of claim 29, "A content addressable memory (CAM) system," is a limiting element. The patent is directed to solving a multi-hit problem specific to CAMs. The accused products are ReRAM, a different class of memory. The analysis will question whether a ReRAM read circuit can be considered a "CAM system" within the meaning of the claim.
- Technical Questions: The complaint maps the claim's two-step "set... and subsequently change" process to the accused read circuit's operation of first setting a reference voltage and then allowing the memory cell to alter that voltage. A central technical question is whether this standard memory read operation performs the specific functions required by the claim, or if the claim, when read in light of the specification, requires a circuit structure and operation specific to priority encoding (e.g., dynamic NOR logic) that is absent from the accused device.
V. Key Claim Terms for Construction
The Term: "content addressable memory (CAM) system"
- Context and Importance: This term appears in the preamble of the asserted independent claim. Its interpretation is critical because if it is deemed limiting, the Plaintiff must prove that the accused ReRAM products, which are not conventional CAMs, fall within the scope of this term.
- Intrinsic Evidence for a Broader Interpretation: The body of claim 29 recites a generic "circuit segment" and its functional behavior (setting and changing a node's logic level) without explicitly requiring CAM-specific comparison logic. A party could argue the preamble is merely a statement of intended use and not a structural or functional limitation on the claimed circuit segment itself.
- Intrinsic Evidence for a Narrower Interpretation: The patent’s title, abstract, and background are exclusively focused on solving the multi-hit priority encoding problem in CAMs. (’259 Patent, Abstract; col. 1:18-32). A party may argue that this consistent focus requires the claim to be construed as limited to the CAM context.
The Term: "set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs"
- Context and Importance: This language defines the core two-part function of the claimed "circuit segment." The infringement case depends on whether the accused ReRAM read operation can be accurately characterized by this sequence.
- Intrinsic Evidence for a Broader Interpretation: A party could argue this language broadly covers any circuit that establishes an initial state on a node and then modifies that state based on further inputs. The complaint’s theory relies on such a broad reading, mapping "set" to the activation of a read-enable signal and "change" to the activation of a word line. (Compl. p. 14-15).
- Intrinsic Evidence for a Narrower Interpretation: The specification describes implementing this logic using pre-charge and discharge cycles in dynamic logic circuits. (’259 Patent, col. 4:50-68; col. 5:30-41). A party could argue that the term should be limited to this type of operation, which may differ fundamentally from the analog voltage sensing in the accused ReRAM read circuit.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement of infringement, stating that Defendant’s customers infringe by using the accused devices, which contain the circuitry for reading data. It further alleges this use is not a staple article of commerce suitable for substantial non-infringing use. (Compl. ¶23).
- Willful Infringement: While the term "willful" is not used, the complaint alleges pre-suit knowledge. It states that on September 9, 2023, the Plaintiff contacted Defendant’s CEO to "inform him their company's ReRAM... has infringed." (Compl. ¶9). This allegation of actual notice could be used to support a future claim for willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "content addressable memory (CAM) system," which originates from the patent's focus on resolving multi-hit search results, be construed to cover the accused general-purpose ReRAM products, which operate on a different technological principle?
- A key evidentiary question will be one of technical characterization: does the accused ReRAM read circuit's operation—establishing a reference voltage and then sensing a change based on a cell's resistance—constitute the specific, two-step "set... and subsequently change" logical function required by Claim 29, or is this a misapplication of the claim language to a fundamentally different electronic process?