DCT

5:25-cv-02389

SanDisk Corp v. Ipvalue Management Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:25-cv-02389, N.D. Cal., 03/07/2025
  • Venue Allegations: Plaintiff Sandisk alleges venue is proper because a substantial part of the events occurred in the Northern District of California, where Defendant IPValue is headquartered, and because both defendants are subject to personal jurisdiction in the district based on licensing activities directed at California residents.
  • Core Dispute: Plaintiff seeks a declaratory judgment that its 3D NAND flash memory products do not infringe five U.S. patents asserted by Defendants related to semiconductor memory transistor structure, reference voltage determination, and charge pump circuits.
  • Technical Context: The dispute centers on the fundamental design and operation of non-volatile flash memory, a ubiquitous technology for data storage in solid-state drives (SSDs), memory cards, and embedded systems.
  • Key Procedural History: This action follows a lawsuit filed by Defendants on January 22, 2025, in the Central District of California against Sandisk’s former parent company, Western Digital, asserting the same five patents. The complaint states that Defendants’ infringement contentions against Western Digital were based on technology and dies created by Sandisk, creating a direct and immediate controversy between Sandisk and Defendants.

Case Timeline

Date Event
2002-10-29 ’505 Patent Priority Date
2005-11-08 ’505 Patent Issue Date
2007-05-10 ’664 Patent Priority Date
2007-05-25 ’537, ’240, ’365 Patents Priority Date
2010-03-02 ’664 Patent Issue Date
2014-01-21 ’537 Patent Issue Date
2018-03-27 ’240 Patent Issue Date
2021-03-26 Defendants initiate licensing discussions with Western Digital
2022-09-27 ’365 Patent Issue Date
2024-07-01 Defendants send further correspondence to Western Digital
2025-01-22 Defendants sue Western Digital in C.D. Cal.
2025-02-24 Sandisk formally completes spin-off from Western Digital
2025-03-07 Complaint for Declaratory Judgment Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,633,537 - "Memory Transistor with Multiple Charge Storing Layers and a High Work Function Gate Electrode"

  • Patent Identification: U.S. Patent No. 8,633,537, "Memory Transistor with Multiple Charge Storing Layers and a High Work Function Gate Electrode," issued January 21, 2014.

The Invention Explained

  • Problem Addressed: The patent’s background describes a fundamental trade-off in non-volatile memory design affecting data retention. Memory transistors using a silicon-rich charge trapping layer have a large initial performance window but lose charge quickly, while those with a high-quality nitride layer retain charge better but have a smaller initial performance window. (’537 Patent, col. 1:40-col. 2:7).
  • The Patented Solution: The invention proposes an engineered "oxide-nitride-nitride-oxide (ONNO) stack" for the memory transistor. This stack includes a multi-layer charge-trapping region with two distinct nitride layers: a first "oxygen-rich" nitride layer and a second "oxygen-lean" nitride layer. This composite structure is intended to provide both improved data retention and a longer transistor lifetime. (’537 Patent, Abstract; col. 2:25-37).
  • Technical Importance: This approach represents an effort to overcome a key scaling challenge for flash memory by optimizing the physical structure of the charge-trapping layer to improve both performance and long-term reliability. (’537 Patent, col. 2:8-13).

Key Claims at a Glance

  • The complaint asserts non-infringement of all claims and specifically references limitations found in the independent claims, such as Claim 17. (Compl. ¶¶32-33).
  • Independent Claim 17 essential elements:
    • A vertical channel comprising polysilicon.
    • An ONNO stack disposed about the vertical channel, which comprises:
      • A tunnel dielectric layer.
      • A multi-layer charge-trapping region with two distinct nitride layers: a first "oxygen-rich nitride" layer and a second "silicon-rich, oxygen-lean nitride" layer.
      • A blocking dielectric layer.
    • A high work function gate electrode.

U.S. Patent No. 9,929,240 - "Memory Transistor with Multiple Charge Storing Layers and a High Work Function Gate Electrode"

  • Patent Identification: U.S. Patent No. 9,929,240, "Memory Transistor with Multiple Charge Storing Layers and a High Work Function Gate Electrode," issued March 27, 2018.

The Invention Explained

  • Problem Addressed: Similar to the ’537 Patent, this patent addresses the problem of poor data retention in conventional non-volatile memory cells, which limits transistor lifetime. (’240 Patent, col. 1:50-col. 2:6).
  • The Patented Solution: The invention describes a memory device with a multi-layer charge trapping layer that includes a first dielectric layer of "oxygen-rich nitride" and a second dielectric layer of "oxygen-lean nitride." The specification also discloses an "anti-tunneling layer" disposed between the first and second dielectric layers, intended to further improve performance. (’240 Patent, Abstract).
  • Technical Importance: This technology aims to enhance the reliability of flash memory by engineering the material composition of the charge storage layers to better control electron trapping and leakage. (’240 Patent, col. 2:7-13).

Key Claims at a Glance

  • The complaint asserts non-infringement of all claims and specifically references limitations found in independent claims, such as Claim 12. (Compl. ¶¶36-37).
  • Independent Claim 12 essential elements:
    • A gate structure.
    • A channel positioned between a first and second diffusion region.
    • A tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate and channel.
    • The multi-layer charge trapping layer comprises a "first dielectric layer" of "oxygen-rich nitride" abutting a "second dielectric layer" of "oxygen-lean nitride".

U.S. Patent No. 11,456,365 - "Memory transistor with multiple charge storing layers and a high work function gate electrode"

  • Patent Identification: U.S. Patent No. 11,456,365, "Memory transistor with multiple charge storing layers and a high work function gate electrode," issued September 27, 2022. (Compl. ¶25).
  • Technology Synopsis: This patent, from the same family as the ’537 and ’240 patents, also addresses data retention in non-volatile memory. It discloses a memory device where the multi-layer charge storing region is formed in a "substantially annular shape" surrounding the tunnel dielectric layer, a configuration relevant to vertical or 3D memory architectures. (’365 Patent, Abstract; col. 22:2-6).
  • Asserted Claims: The complaint refers to the independent claims, citing language from Claim 35. (Compl. ¶41).
  • Accused Features: The complaint alleges non-infringement by Sandisk products, including "SanDisk SD cards including 96 layer or 112 layer 3D NAND Flash memory," focusing on the physical structure of the charge storing region. (Compl. ¶¶18, 41).

U.S. Patent No. 6,963,505 - "Method Circuit and System For Determining a Reference Voltage"

  • Patent Identification: U.S. Patent No. 6,963,505, "Method Circuit and System For Determining a Reference Voltage," issued November 8, 2005. (Compl. ¶27).
  • Technology Synopsis: This patent addresses the problem of threshold voltage drift in memory cells, which can cause read errors. It discloses a method to dynamically find an optimal reference voltage for reads by testing multiple possible reference levels on a subset of cells and selecting the level that yields the lowest read error rate. (’505 Patent, Abstract).
  • Asserted Claims: The complaint identifies Claim 1 as the independent claim asserted by Defendants. (Compl. ¶45).
  • Accused Features: The complaint alleges non-infringement by products such as the "96L 3D TLC SanDisk die." The dispute centers on the method of setting read voltages, with Sandisk denying that its products perform the claimed step of determining a read error rate for each possible reference level. (Compl. ¶¶18, 45).

U.S. Patent No. 7,671,664 - "Charge Pump Control Circuit and Method"

  • Patent Identification: U.S. Patent No. 7,671,664, "Charge Pump Control Circuit and Method," issued March 2, 2010. (Compl. ¶29).
  • Technology Synopsis: This patent addresses the need for charge pump circuits that offer both fast voltage startup and low power consumption during steady-state operation. The invention is a control circuit that uses a high-frequency clock to quickly reach the desired voltage at startup and then switches to a low-frequency clock, but periodically uses the high-frequency clock for brief intervals to maintain the voltage level efficiently. (’664 Patent, Abstract).
  • Asserted Claims: The complaint identifies Claim 1 as the independent claim asserted by Defendants. (Compl. ¶49).
  • Accused Features: The complaint alleges non-infringement by circuits such as the "Toshiba/SanDisk TP70G7AWV 96-layer 3D NAND Flash Circuit." Sandisk contends that the "output" of the accused "clock control circuit" is not "based on a dynamic load" as the claim requires. (Compl. ¶¶18, 49-50).

III. The Accused Instrumentality

Product Identification

  • The complaint seeks a declaration of non-infringement for Sandisk products including "SSDs, OptiNAND HDDs, USB Flash Drives, Embedded Flash, and Memory Cards containing 3D NAND flash memory." (Compl. ¶18). Specific accused components include various "SanDisk die" and "SanDisk 3D NAND Flash" parts. (Compl. ¶18).

Functionality and Market Context

  • The accused instrumentalities are non-volatile memory products that store digital data. The complaint alleges that the purportedly infringing functionality resides not in end-user features but in the underlying physical structure and operation of the semiconductor memory dies manufactured by Sandisk. (Compl. ¶18). These components are foundational to a wide range of consumer and enterprise electronics. (Compl. ¶14).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

This declaratory judgment action asserts non-infringement. The following tables summarize the plaintiff's stated bases for why its products do not meet the claim limitations.

U.S. Patent No. 8,633,537 Infringement Allegations

Claim Element (from Independent Claim 17) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a multi-layer charge-trapping region including a first nitride layer comprising an oxygen-rich nitride... and a second nitride layer comprising a silicon-rich, oxygen-lean nitride... Sandisk’s products do not have a multi-layer charge-trapping region with a first nitride layer and a second nitride layer as specified in the claim. ¶33 col. 2:32-37

U.S. Patent No. 9,929,240 Infringement Allegations

Claim Element (from Independent Claim 12) Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a multi-layer charge trapping layer comprises a first dielectric layer disposed abutting a second dielectric layer, wherein the first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride. Sandisk's products do not have a multi-layer charge-trapping layer with a first dielectric layer and a second dielectric layer as specified in the claim. ¶37 col. 9:10-18

Identified Points of Contention

  • Technical Questions: The core of the dispute for the ’537 and ’240 patents appears to be a factual one regarding the physical composition of Sandisk's 3D NAND memory cells. The central question is whether the charge trapping layer in the accused products is a single homogenous layer or if it constitutes the specific two-layer structure of differing nitride compositions as claimed.
  • Scope Questions: The analysis for the ’537 and ’240 patents will raise the question of how the terms "oxygen-rich" and "oxygen-lean" should be construed. The dispute may turn on what degree of compositional difference is required to meet these claim limitations and whether Sandisk's manufacturing process results in such a difference. For the ’505 patent, a key question is whether the accused products’ voltage calibration method performs the specific step of "determining a read error rate for each one of said possible reference levels," or if it uses a different, non-infringing algorithm. (Compl. ¶45).

V. Key Claim Terms for Construction

  • The Term: "a multi-layer charge-trapping region including a first nitride layer comprising an oxygen-rich nitride... and a second nitride layer comprising a... silicon-rich, oxygen-lean nitride" (’537 Patent, Claim 17).
  • Context and Importance: This term is central to the dispute for the ’537, ’240, and ’365 patents. Sandisk’s primary non-infringement argument is that its products do not contain this specific two-part structure. (Compl. ¶¶33, 37, 41). Practitioners may focus on this term because its construction will determine whether a single, compositionally-graded nitride layer could infringe, or if two physically and compositionally distinct layers are required.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the function of the two layers as creating different charge trapping characteristics to improve data retention. (’537 Patent, col. 1:40-col. 2:7). A party might argue that any structure with functionally distinct regions, even if not physically separate layers, could meet this limitation.
    • Evidence for a Narrower Interpretation: The patent repeatedly refers to a "first nitride layer" and a "second nitride layer," and the summary of the invention describes the second layer as being "disposed above the first nitride layer." (’537 Patent, col. 2:32-35). Figure 4A depicts two distinct layers (422a, 422b), which may support a narrower construction requiring two physically separate layers.

VI. Other Allegations

Indirect Infringement

  • The complaint seeks a judgment of non-infringement for direct infringement as well as contributory infringement and inducement. (Demand for Relief ¶(1)). The complaint does not, however, detail the specific allegations Defendants may have made to support claims of indirect infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A core issue will be one of structural identity: Does the charge-trapping region in Sandisk’s 3D NAND products consist of the specific two-layer nitride structure with differing oxygen and silicon compositions as required by the ’537, ’240, and ’365 patents, or is it a structurally different design? This question combines claim construction with a factual, evidence-intensive inquiry into semiconductor physics and fabrication.
  2. A second key issue will be one of functional operation: Do the control circuits in Sandisk's products operate in the specific manner claimed by the ’505 and ’664 patents? This raises the evidentiary question of whether the accused products perform the precise algorithm of determining a read error rate for each possible reference level (’505 Patent) and whether the clock control signal is functionally "based on a dynamic load" (’664 Patent), or if they achieve similar results through technically distinct, non-infringing methods.