DCT

3:17-cv-00462

Macronix Intl Co Ltd v. Toshiba Corp

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 3:17-cv-00462, S.D. Cal., 03/07/2017
  • Venue Allegations: Venue is alleged to be proper in the Southern District of California because the U.S. defendants are California corporations with headquarters in Irvine, California, and all defendants are subject to personal jurisdiction and have allegedly committed acts of infringement in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s non-volatile memory (NVM) devices, including NAND flash memory chips and products containing them, infringe three patents related to semiconductor circuit layout, memory device operation, and output buffer circuits.
  • Technical Context: The patents relate to fundamental aspects of semiconductor design and manufacturing, including methods to improve manufacturing yield, prevent data errors in memory arrays, and manage power output in integrated circuits.
  • Key Procedural History: The complaint alleges that Plaintiff Macronix provided Defendant Toshiba with notice of infringement of the ’360 Patent on April 2, 2015, and of the ’602 and ’417 Patents on January 14, 2016, through a series of discussions that included the presentation of exemplary claim charts.

Case Timeline

Date Event
2002-01-25 Priority Date for U.S. Patent No. 6,552,360
2002-08-09 Priority Date for U.S. Patent No. 6,788,602
2003-04-22 U.S. Patent No. 6,552,360 Issues
2004-09-07 U.S. Patent No. 6,788,602 Issues
2010-07-26 Priority Date for U.S. Patent No. 8,035,417
2011-10-11 U.S. Patent No. 8,035,417 Issues
2015-04-02 Macronix allegedly notifies Toshiba of ’360 Patent infringement
2016-01-14 Macronix allegedly notifies Toshiba of ’602 & ’417 Patent infringement
2017-03-07 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,552,360, “Method and Circuit Layout for Reducing Post Chemical-Mechanical Polishing Defect Count,” Issued April 22, 2003

The Invention Explained

  • Problem Addressed: During semiconductor manufacturing, a process called Chemical-Mechanical Polishing (CMP) is used to planarize, or flatten, layers on a wafer. The patent states that this process can exert uneven pressure on the front and rear ends of parallel circuit structures, causing physical damage and defects that reduce manufacturing yield and device performance (’360 Patent, col. 1:49-65, col. 2:1-5).
  • The Patented Solution: The invention proposes a new circuit layout that adds at least two "second circuit structure" strips (130b) to link the front and rear ends of the primary "first circuit structure" strips (130a) (’360 Patent, Abstract; col. 2:25-34). These linking strips are intended to improve the structural strength of the layout and average the polishing pressure across the ends of the primary circuit strips, thereby reducing the likelihood of CMP-induced defects (’360 Patent, col. 4:24-43). The complaint includes a figure from the patent illustrating this layout concept, where arrows represent the polishing pressure. (Compl. ¶24, p. 8; ’360 Patent, Fig. 4).
  • Technical Importance: In an era of increasing circuit density, improving manufacturing yield by reducing process-related defects like those from CMP was a critical concern for semiconductor manufacturers. (Compl. ¶¶15, 17-18).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claim 2. (Compl. ¶46).
  • Independent Claim 1 requires:
    • A circuit layout on a substrate of a semiconductor wafer
    • A plurality of strips of a first circuit structure
    • At least two strips of a second circuit structure
    • Wherein each of the two strips of the second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure
    • Utilizing this layout to average polishing pressure during a CMP process to reduce defects
  • The complaint reserves the right to assert other claims. (Compl. ¶46).

U.S. Patent No. 6,788,602, “Memory Device and Operation Thereof,” Issued September 7, 2004

The Invention Explained

  • Problem Addressed: In memory arrays, word lines at the edge of the array are often "dummy" lines not used for data storage, to protect usable memory cells from damage during fabrication. The patent explains that if these dummy word lines are coupled to ground, they can become "over-erased" during repeated program/erase cycles, leading to current leakage along the associated bit lines that can corrupt read operations of usable memory cells (’602 Patent, col. 1:23-36).
  • The Patented Solution: The invention proposes a memory device and method where the dummy word line is coupled to a "positive bias" instead of ground, at least during an erase operation (’602 Patent, Abstract). Applying this positive voltage is intended to prevent the dummy cells from being over-erased, thereby reducing the associated current leakage and improving the reliability of the memory device over its operational life (’602 Patent, col. 2:5-10).
  • Technical Importance: As non-volatile memory (NVM) became standard for data storage, ensuring device reliability and endurance over many thousands of write/erase cycles was a key technical challenge. (Compl. ¶17; '602 Patent, col. 1:37-44).

Key Claims at a Glance

  • The complaint asserts independent claims 1, 7, and 11, and dependent claims 6, 9, and 12. (Compl. ¶51).
  • Independent Claim 1 requires:
    • A semiconductor memory device comprising a memory cell
    • A dummy word line arranged at an edge of a memory array and coupled to the memory cell
    • A control logic for supplying a positive bias to the dummy word line during an erase operation
    • At least one bit line coupled to the memory cell
  • The complaint reserves the right to assert other claims. (Compl. ¶51).

Multi-Patent Capsule

  • Patent Identification: U.S. Patent No. 8,035,417, “Output Buffer Circuit with Variable Drive Strength,” Issued October 11, 2011. (Compl. ¶30).
  • Technology Synopsis: The patent addresses the problem that designing custom output buffer circuits for every electrical load is complicated (’417 Patent, col. 1:11-15). The invention discloses an output buffer circuit with a variable drive strength that can be set based on control signals, allowing a single design to be adapted for different purposes, supply voltages, and loads (’417 Patent, Abstract; Compl. ¶¶34-35).
  • Asserted Claims: The complaint asserts independent claims 1, 11, and 18. (Compl. ¶56).
  • Accused Features: The complaint alleges that Toshiba’s NVM chips, such as the TH58TEG8DDKBA8C, infringe by incorporating output buffer circuits that practice the claimed invention. (Compl. ¶56).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are certain non-volatile memory ("Accused NVM") devices, specifically NAND flash memory chips, and the broader category of "Accused Products" which contain these NVMs. (Compl. ¶¶16-17). Named accused NVMs include Toshiba's TC58NVG1S3HTA00, TC58NVG3S0FTA00, TH58TEG7DCJTA20, TC58NVG4D2FTA00, and TH58TEG8DDKBA8C. (Compl. ¶¶20, 46, 51, 56).

Functionality and Market Context

The Accused NVMs are used for data storage in a wide array of consumer and industrial electronics. (Compl. ¶17). The complaint references a promotional image from Toshiba's website for the Flash Memory Summit, which shows its storage products targeted at enterprise, data center, automotive, industrial, mobile, and client applications. (Compl. ¶12, p. 5). A separate marketing diagram from Toshiba's website, also included in the complaint, illustrates that its NAND flash memories are used in products such as wearable devices, digital camcorders, mobile devices, advanced audiovisual systems, car navigation systems, and servers. (Compl. ¶44, p. 12). The complaint alleges that Toshiba manufactures its NAND flash memories at its Yokkaichi Operations in Japan and that these are sold in the U.S. through distributors. (Compl. ¶¶8-9).

IV. Analysis of Infringement Allegations

The complaint states that exemplary claim charts are provided in confidential exhibits that were filed under seal and are not available for review. (Compl. ¶¶47, 52, 57). The infringement allegations are therefore summarized below based on the narrative in the complaint.

’360 Patent Infringement Allegations

The complaint alleges that Toshiba’s NVMs, including the TC58NVG4D2FTA00 and TH58TEG7DCJTA20 chips, directly infringe at least claims 1 and 2 of the ’360 Patent. (Compl. ¶46). The infringement theory appears to be based on the physical layout of the accused chips, alleging that they embody the claimed circuit structure designed to reduce defects during the CMP manufacturing process. (Compl. ¶49).

Identified Points of Contention

  • Technical Question: A central question will be whether the accused Toshiba chips contain a "second circuit structure" that performs the specific function recited in the claims: linking the front and rear ends of a "first circuit structure" for the purpose of averaging polishing pressure. Evidence will likely require analysis of the physical chip layout.
  • Scope Question: The parties may dispute whether structures present in the accused chips, which may have other primary functions, can also be characterized as the claimed "second circuit structure."

’602 Patent Infringement Allegations

The complaint alleges that Toshiba’s NVMs, including the TH58TEG8DDKBA8C chip, directly infringe at least claims 1, 6, 7, 9, 11, and 12 of the ’602 Patent. (Compl. ¶51). The infringement theory is that the accused devices contain dummy cells coupled to dummy word lines that are prevented from over-erasing in a manner that practices the claimed invention. (Compl. ¶¶53-54).

Identified Points of Contention

  • Technical Question: A key factual issue will be whether the accused devices' control logic actually supplies a "positive bias" to the alleged "dummy word line" during an erase operation, as required by the claims. This may turn on evidence from device datasheets or direct testing of the accused chips.
  • Scope Question: Does the term "dummy word line" as used in the patent, which is described as a word line not used for programming, read on the specific edge-of-array structures in the accused devices?

V. Key Claim Terms for Construction

For the ’360 Patent

  • The Term: "second circuit structure" (Claim 1)
  • Context and Importance: The entire infringement theory for the '360 Patent hinges on the presence of this structure. Its construction will determine whether ancillary or unrelated layout features in the accused device could be found to meet this limitation, or if it must be a structure specifically designed for and capable of averaging polishing pressure.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims do not limit the physical composition of the structure, stating only that it links the front and rear ends of the first circuit structure. Claim 7 suggests it can be comprised of the same layers as the first circuit, "a conductive layer and an insulating layer." (’360 Patent, col. 6:28-31).
    • Evidence for a Narrower Interpretation: The specification repeatedly ties the structure to a specific purpose: "utilizing to average polishing pressure" (’360 Patent, col. 2:29-34; col. 5:10-16). Figure 4 shows the structure as a distinct bar connecting the ends of other parallel strips, suggesting a specific geometry. A defendant may argue this purpose and geometry are required limitations.

For the ’602 Patent

  • The Term: "positive bias" (Claim 1)
  • Context and Importance: Infringement requires supplying a "positive bias" to the dummy word line. Practitioners may focus on this term because its definition—whether it means any voltage greater than zero, or a specific voltage relative to other potentials in the circuit—will be critical.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term is not explicitly defined with a numerical range. The specification contrasts the invention with the prior art practice of coupling the dummy word line to "ground," which implies "positive bias" could mean any voltage potential greater than ground. (’602 Patent, col. 1:30-31).
    • Evidence for a Narrower Interpretation: The embodiments describe specific positive voltages (e.g., "2.6 volts," "3.7 volts") supplied during an erase operation, while noting that a bias of "0 volts" may be used during programming operations. (’602 Patent, col. 4:55-60; col. 5:21-23). A defendant could argue these examples limit "positive bias" to a non-zero voltage applied specifically during the erase cycle.

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement of infringement for all three patents. (Compl. ¶¶48, 53, 58). The allegations are based on Toshiba providing customers with the Accused NVMs along with technical documentation, datasheets, application notes, and white papers that allegedly instruct customers on how to operate the products in an infringing manner. (Compl. ¶¶45, 54, 58). The complaint points to Toshiba's product documentation, which allegedly instructs customers on how to use the products and their various operating parameters, such as voltage specifications. (Compl. ¶¶13, 45, p. 12-13). Contributory infringement is also alleged, on the basis that the accused NVMs are specially made to infringe and are not staple articles with substantial non-infringing uses. (Compl. ¶¶49, 54, 59).

Willful Infringement

The complaint alleges willful infringement for all three patents. (Compl. ¶¶50, 55, 60). The allegations are based on pre-suit knowledge stemming from discussions between Macronix and Toshiba, where Macronix allegedly provided notice of infringement of the '360 Patent on April 2, 2015, and of the '602 and '417 Patents on January 14, 2016. (Compl. ¶41).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A question of structural identity: For the ’360 Patent, the core dispute will be whether Toshiba’s NAND flash memory chips, designed for high-density storage, contain physical layouts that can be properly characterized as having the "second circuit structure" whose purpose, as described in the patent, is to solve a specific manufacturing problem (CMP defects). This raises the question of whether a structure must be intended for the patented purpose to infringe.
  2. A question of operational function: For the ’602 Patent, the case will likely turn on an evidentiary question of how the accused memory devices actually operate. Does Toshiba’s control logic apply a "positive bias" to edge-of-array word lines during an erase cycle, and if so, does this operation map onto the specific method claimed for preventing over-erasure of dummy cells?
  3. A question of knowledge and intent: Given the allegations of pre-suit notice and discussions between the parties, the court will likely examine the extent of Toshiba's knowledge regarding the patents-in-suit. The specific content of the alleged discussions and claim charts exchanged will be central to resolving the claims for willful and indirect infringement.