3:22-cv-01527
Bell Semiconductor LLC v. NXP USA Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: NXP USA, Inc. (USA, principal place of business in Texas)
- Plaintiff’s Counsel: Yukevich Cavanaugh; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 3:22-cv-01527, S.D. Cal., 10/06/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendant has a regular and established place of business in the Southern District of California, employs engineers there, advertises jobs relevant to the patented technology in the district, and has committed acts of infringement in the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal processes for designing semiconductor chips, such as the NXP LS1043A processor, infringe a patent related to methods for efficiently implementing engineering changes in integrated circuit designs.
- Technical Context: The lawsuit concerns the field of electronic design automation (EDA), where software tools are used to manage the immense complexity of modern integrated circuit (IC) design and fabrication.
- Key Procedural History: The complaint asserts ownership of a large portfolio of semiconductor-related patents originating from Bell Labs and its successors, including LSI Corporation, and notes that the patent-in-suit was assigned to the Plaintiff. No prior litigation or post-grant proceedings involving the patent-in-suit are mentioned in the complaint.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | ’626 Patent Priority Date (Application Filing) |
| 2007-06-12 | ’626 Patent Issue Date |
| 2022-10-06 | Complaint Filing Date |
| 2025-07-26 | ’626 Patent Expiration Date (as alleged in complaint) |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows
- Patent Identification: U.S. Patent No. 7,231,626, Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows, issued June 12, 2007 (’626 Patent).
The Invention Explained
- Problem Addressed: In prior methods of integrated circuit design, implementing even a minor engineering change order (ECO) was highly inefficient. Design tools for processes like cell placement, routing, and design rule verification had to be run for the entire circuit design, which could take a week or more, regardless of the change's small size ('626 Patent, col. 2:14-23; Compl. ¶¶2-3).
- The Patented Solution: The invention proposes a method to accelerate this process by defining a "window" that spatially encloses only the portion of the circuit design affected by the ECO. Subsequent, resource-intensive design steps, such as routing, are then performed only on the electrical nets contained within this smaller window, rather than across the entire chip design ('626 Patent, Abstract, col. 3:58-62). The process flow shown in Figure 2 of the patent illustrates this window-based, incremental approach as a more efficient alternative to the full-chip process flow shown in Figure 1 ('626 Patent, FIG. 1, FIG. 2).
- Technical Importance: This "windowing" method claims to realize "significant savings in the resources required to perform routing, design rule check verification, net delay calculation, and parasitic extraction," thereby shortening design timelines and reducing costs ('626 Patent, col. 3:19-23; Compl. ¶27).
Key Claims at a Glance
- The complaint quotes independent claim 1 and notes the patent contains two independent claims (Compl. ¶30). The independent claims are method claim 1 and computer-readable medium claim 5.
- Independent Claim 1 (Method):
- (a) receiving as input an integrated circuit design;
- (b) receiving as input an engineering change order to the integrated circuit design;
- (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design;
- (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window;
- (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and
- (f) generating as output the revised integrated circuit design.
- The complaint implicitly reserves the right to assert other claims by stating NXP infringes "one or more claims" (Compl. ¶37).
III. The Accused Instrumentality
Product Identification
The complaint identifies the "Accused Processes" as the methodologies NXP uses to design its semiconductor devices, with the "NXP LS1043A Quad-Core Networking Processor" cited as an exemplary product manufactured using these processes (Compl. ¶¶9, 38).
Functionality and Market Context
The complaint alleges that NXP utilizes a variety of third-party EDA tools from vendors like Cadence, Synopsys, and/or Siemens to implement its design processes (Compl. ¶38). The accused functionality is NXP's alleged use of these tools to perform incremental, or "windowed," design modifications. Specifically, when implementing an ECO, NXP is alleged to perform routing, parasitic extraction, and design rule checks "only for each net in the IC design enclosed by the window defining the ECO" (Compl. ¶¶38-40).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint. While the complaint refers to an exemplary infringement analysis in an "Exhibit B," that exhibit is not attached to the filed document (Compl. ¶41). The analysis below is based on the narrative allegations in the complaint body.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | NXP's Accused Processes receive an integrated circuit design as an input for modification (implicit in the overall allegation). | ¶38 | col. 6:1-2 |
| (b) receiving as input an engineering change order to the integrated circuit design; | NXP's Accused Processes receive an ECO for implementation in the design. | ¶38 | col. 6:3-5 |
| (c) creating at least one window... that is less than an entire area of the integrated circuit design; | The Accused Processes are alleged to define a window for the ECO, which is then used for subsequent steps like routing, parasitic extraction, and design rule checks. | ¶¶39-40 | col. 6:6-12 |
| (d) performing an incremental routing... only for each net... that is enclosed by the window; | NXP allegedly employs design tools to "perform a method for only routing the nets affected by the ECO." | ¶38 | col. 6:29-34 |
| (e) replacing an area in a copy... with results of the incremental routing to generate a revised integrated circuit design; | NXP's process is alleged to merge the "changed area into the overall circuit layout... to generate a revised integrated circuit design." | ¶¶38, 10 | col. 6:35-40 |
| (f) generating as output the revised integrated circuit design. | The end result of NXP's Accused Processes is a "revised integrated circuit design." | ¶10 | col. 6:41-43 |
Identified Points of Contention
- Factual Question: The complaint's allegations regarding the internal workings of NXP's design process are made "on information and belief" (Compl. ¶37). A central question for discovery will be whether NXP's use of third-party EDA tools for implementing ECOs actually aligns with the specific sequence and limitations of the asserted claims.
- Scope Question: The claim requires performing routing "only for each net... that is enclosed by the window." The case may turn on the factual and legal interpretation of "only." The court may need to determine if NXP's accused processes perform any routing-related functions on nets outside the defined window and, if so, whether such functions fall outside the scope of this negative limitation.
V. Key Claim Terms for Construction
The Term: "window"
Context and Importance: This term is the central pillar of the invention. Its construction will determine whether the method by which NXP's design tools isolate areas for changes constitutes an infringing "window."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent provides a general definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" ('626 Patent, col. 3:58-62). This could support a construction that is not tied to a specific method of creation.
- Evidence for a Narrower Interpretation: The specification also provides a detailed flowchart (FIG. 3) for a specific method of "creating an engineering change order window," which involves calculating bounding boxes around specific port instances ('626 Patent, col. 4:54-56). A defendant may argue that the term should be limited to windows created by such specific, disclosed algorithms.
The Term: "performing an incremental routing... only for each net... that is enclosed by the window"
Context and Importance: The negative limitation "only" is a critical constraint on the scope of the claim. Infringement will depend on whether NXP's accused processes meet this strict condition.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation (favoring infringement): The specification contrasts the invention with the prior art, where "a routing of the entire integrated circuit design is performed" ('626 Patent, col. 2:64-65). A plaintiff may argue "only" should be interpreted in light of this contrast, meaning the main, substantive routing operation is confined to the window, even if minor, ancillary checks occur elsewhere.
- Evidence for a Narrower Interpretation (favoring non-infringement): A defendant may argue that "only" must be given its plain and absolute meaning. If discovery reveals that NXP's design tools perform any routing, re-routing, or routing-adjacent analysis on even a single net outside the defined window as part of the ECO implementation, it could support a non-infringement argument.
VI. Other Allegations
- Indirect Infringement: The complaint makes a conclusory allegation of indirect infringement (Compl. ¶43) but does not plead specific facts to support a claim of either induced or contributory infringement, such as NXP providing instructions or components to a third party to perform the patented method. The core of the complaint focuses on NXP's own direct use of the accused design processes.
- Willful Infringement: The complaint does not contain a specific count for willful infringement or allege pre-suit knowledge of the patent. It does, however, allege that NXP's infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285, which suggests an intent to pursue a finding of post-suit willfulness or other litigation misconduct (Compl. ¶44).
VII. Analyst’s Conclusion: Key Questions for the Case
The resolution of this dispute will likely depend on the answers to two central questions:
A core issue will be one of evidentiary proof: Can Bell Semiconductor, through discovery, produce factual evidence demonstrating that NXP’s internal design methodologies, which rely on complex third-party EDA software, practice each specific step of the patented method? The "information and belief" pleading standard will need to be substantiated with proof of how NXP's processes actually operate.
A key legal and factual question will be one of functional boundaries: Does NXP’s accused design process perform routing and other checks "only" on nets within a defined area, as required by the claim? The case will likely involve a granular analysis of NXP's process flows to determine if any operations on nets outside a "window" are sufficient to negate infringement of this critical limitation.